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Preliminary Data Sheet April 2004
TruePHY TM ET1011 Gigabit Ethernet Transceiver
Features
Introduction
Agere Systems ET1011 is a gigabit Ethernet transceiver fabricated on a single CMOS chip. Packaged in either a 128-pin TQFP or a 68-pin MLCC, the ET1011 is built on 0.13 m technology for low power consumption and application in server and desktop NIC cards. It features single power supply operation using on-chip regulator controllers. The 10/100/ 1000Base-T device is fully compliant with IEEE(R) 802.3, 802.3u, and 802.3ab standards. The ET1011 uses an oversampling architecture to gather more signal energy from the communication channel than possible with traditional architectures. The additional signal energy or analog complexity transfers into the digital domain. The result is an analog front end that delivers robust operation, reduced cost, and lower power consumption than traditional architectures. Using oversampling has allowed for the implementation of a fractionally spaced equalizer, which provides better equalization and has greater immunity to timing jitter, resulting in better signal-to-noise ratio (SNR) and thus improved BER. In addition, advanced timing algorithms are used to enable operation over a wider range of cabling plants.
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10Base-T, 100Base-TX, and 1000Base-T gigabit Ethernet transceiver: -- 0.13 m process -- 128-pin TQFP: RGMII, GMII, MII, RTBI, and TBI interfaces to MAC or switch -- 68-pin MLCC: RGMII and RTBI interfaces to MAC or switch Low power consumption: -- Less than 750 mW in 1000Base-T mode -- Advanced power management -- ACPI compliant wake-on-LAN support Oversampling architecture to improve signal integrity and SNR Optimized, extended performance echo and NEXT filters All digital baseline wander correction Digital PGA control On-chip diagnostic support Automatic speed negotiation Automatic speed downshift Single supply 3.3 V or 2.5 V operation: -- On-chip regulator controllers -- 3.3 V or 2.5 V digital I/O -- 1.0 V core power supplies -- 1.8 V or 2.5 V for transformer center tap JTAG

TruePHY ET1011 Gigabit Ethernet Transceiver
Preliminary Data Sheet April 2004
Table of Contents
Contents Page Contents Page
Features ...................................................................... 1 Introduction.................................................................. 1 Functional Description ................................................. 4 Oversampling Architecture.................................... 4 Automatic Speed Downshift .................................. 4 Transmit Functions ............................................... 5 Receive Functions ................................................ 5 Autonegotiation ..................................................... 6 Carrier Sense (128-pin TQFP only) ...................... 6 www..com Link Monitor .......................................................... 7 Loopback Mode .................................................... 8 Digital Loopback ................................................... 9 Analog Loopback ................................................ 10 LEDs ................................................................... 11 Resetting the ET1011 ......................................... 11 Low-Power Modes .............................................. 11 Pin Information .......................................................... 12 Pin Diagram, 128-Pin TQFP .............................. 12 Pin Diagram, 68-Pin MLCC ................................ 13 Pin Descriptions, 128-Pin TQFP and 68-Pin MLCC ................................................... 14 Hardware Interfaces .................................................. 20 MAC Interface ..................................................... 21 Management Interface ........................................ 26 Configuration Interface........................................ 28 LEDs Interface .................................................... 32 Media-Dependent Interface: Transformer Interface....................................... 34 Clocking and Reset ............................................. 35 JTAG ................................................................... 36 Regulator Control ................................................ 36 Power, Ground, and No Connect ........................ 37 Cable Diagnostics...................................................... 38 Register Description .................................................. 39 Register Address Map ........................................ 39 Electrical Specifications............................................. 59 Absolute Maximum Ratings ................................ 59 Recommended Operating Conditions ................. 59 Device Electrical Characteristics......................... 60 Timing Specification .................................................. 62 GMII 1000Base-T Transmit Timing (128-pin TQFP only) ........................................ 62 GMII 1000Base-T Receive Timing (128-pin TQFP only) ........................................ 63 RGMII 1000Base-T Transmit Timing .................. 64 RGMII 1000Base-T Receive Timing ................... 66 MII 100Base-TX Transmit Timing ....................... 68 MII 100Base-TX Receive Timing ....................... 69 MII 10Base-T Transmit Timing............................ 70 MII 10Base-T Receive Timing............................. 71 Serial Management Interface Timing .................. 72 Reset Timing ....................................................... 73 2
Clock Timing ....................................................... 74 JTAG Timing ....................................................... 75 Package Diagram, 128-Pin TQFP ............................. 76 Package Diagram, 68-Pin MLCC ............................. 77 Ordering Information.................................................. 78 Related Product Documentation ........................78
Table
Page
Table 1. Agere Systems ET1011 Device Signals by Interface, 128-Pin TQFP and 68-Pin MLCC ........................................ 14 Table 2. Multiplexed Signals on the ET1011 ............ 19 Table 3. GMII Signal Description (1000Base-T Mode) (128-pin TQFP Only) ................................... 21 Table 4. RGMII Signal Description (1000Base-T Mode) .................................... 22 Table 5. MII Interface (100Base-TX and 10Base-T) (128-pin TQFP Only) .................................. 23 Table 6. Ten-Bit Interface (1000Base-T) (128-pin TQFP Only) .................................. 24 Table 7. RTBI Signal Description (1000Base-T Mode)..................................... 25 Table 8. Management Frame Structure .................... 26 Table 9. Management Interface ................................ 27 Table 10. Autonegotiation Modes ............................. 28 Table 11. Master/Slave Preference........................... 29 Table 12. MDI/MDI-X Configuration ......................... 30 Table 13. Configuration Signals ............................... 30 Table 14. LED .......................................................... 33 Table 15. Transformer Interface Signals .................. 34 Table 16. Clocking and Reset .................................. 35 Table 17. JTAG Test Interface ................................. 36 Table 18. Regulator Control Interface ...................... 36 Table 19. Supply Voltage Combinations .................. 37 Table 20. Power, Ground, and No Connect ............. 37 Table 21. Cable Diagnostic Functions ...................... 38 Table 22. Register Address Map .............................. 39 Table 23. Register Type Definition ........................... 39 Table 24. Control Register--Address 0 .................... 40 Table 25. Status Register--Address 1 ..................... 41 Table 26. PHY Identifier Register 1--Address 2 ...... 42 Table 27. PHY Identifier Register 2--Address 3 ...... 42 Table 28. Autonegotiation Advertisement Register--Address 4 ................................ 43 Table 29. Autonegotiation Link Partner Ability Register--Address 5 ................................ 44 Table 30. Autonegotiation Expansion Register-- Address 6 ................................................. 45
Agere Systems Inc.
Preliminary Data Sheet April 2004
TruePHY ET1011 Gigabit Ethernet Transceiver
Table of Contents (continued)
Table Page Table
Table 67. Table 68. Table 69. Table 70 Table 71.
Page
Reset Timing ............................................ 73 Clock Timing ............................................. 74 TAG Timing .............................................. 75 Chip Set Names and Part Numbers ......... 78 Related Product Documentation .............. 78
Table 31. Autonegotiation Next Page Transmit Register--Address 7 ................................ 45 Table 32. Link Partner Next Page Register-- Address 8 ................................................. 46 Table 33. 1000 Base-T Control Register-- Address 9 ................................................. 47 Table 34. 1000Base-T Status Register-- Address 10 ............................................... 48 Table 35. Reserved Registers-- www..com Addresses 11--14 .................................... 49 Table 36. Extended Status Register-- Address 15 ............................................... 49 Table 37. Reserved Registers--Addresses 16--18 . 49 Table 38. Loopback Control Register-- Address 19 ............................................... 50 Table 39. Reserved Registers--Address 20 ............ 51 Table 40. Management Interface (MI) Control Register--Address 21 .............................. 51 Table 41. PHY Configuration Register-- Address 22 ............................................... 52 Table 42. PHY Control Register--Address 23 ......... 53 Table 43. Interrupt Mask Register--Address 24 ...... 54 Table 44. Interrupt Status Register--Address 25 ..... 55 Table 45. PHY Status Register--Address 26 ........... 56 Table 46. LED Control Register 1--Address 27 ....... 57 Table 47. LED Control Register 2--Address 28 ....... 58 Table 48. Reserved Registers--Addresses 29--31 . 58 Table 49. Absolute Maximum Ratings ...................... 50 Table 50. Recommended Operating Conditions ...... 59 Table 51. Device Characteristics--3.3V Digital I/O Supply (DVDDIO) ............................... 60 Table 52. Device Characteristics--2.5 V Digital I/O Supply (DVDDIO) ................................ 60 Table 53. Current Consumption GMII/RGMII 1000Base-T .............................................. 61 Table 54. Current Consumption MII/RMII 100Base-TX ............................................. 61 Table 55. Current Consumption MII/RMII 10Base-T .................................................. 61 Table 56. GMII 1000Base-T Transmit Timing .......... 62 Table 57 GMII 1000Base-T Receive Timing ........... 63 Table 58. RGMII 1000Base-T Transmit Timing ........ 64 Table 59. RGMII 1000Base-T Transmit Timing ........ 65 Table 60. RGMII 1000Base-T Receive Timing ......... 66 Table 61. RGMII 1000Base-T Receive Timing ......... 67 Table 62. MII 100Base-TX Transmit Timing ............. 68 Table 63. MII 100Base-TX Receive Timing .............. 69 Table 64 MII 10Base-T Transmit Timing ................. 70 Table 65. MII 10Base-T Receive Timing .................. 71 Table 66 Serial Management Interface Timing ....... 72
Figure
Page
Figure 1. ET1011 Block Diagram ............................. 4 Figure 2. Loopback Functionality ............................. 8 Figure 3. Digital Loopback ....................................... 9 Figure 4. Replica Analog Loopback .......................10 Figure 5. Line Driver Analog Loopback .................. 10 Figure 6. Pin Diagram for ET1011 in 128-Pin TQFP Package (Top View) ..................... 12 Figure 7. Pin Diagram for ET1011 in 68-Pin MLCC Package (Top View) ................................ 13 Figure 8. ET1011 Gigabit Ethernet Card Block Diagram ........................................ 20 Figure 9. GMII MAC-PHY Signals .......................... 21 Figure 10. RGMII MAC-PHY Signals .......................22 Figure 11. MII Signals .............................................. 23 Figure 12. Ten-Bit Interface ...................................... 24 Figure 13. Reduced Ten-Bit Interface ...................... 25 Figure 14. GMII 1000Base-T Transmit Timing ......... 62 Figure 15. GMII 1000Base-T Receive Timing .......... 63 Figure 16. RGMII 1000Base-T Transmit Timing-- Trace Delay ............................................. 64 Figure 17. RGMII 1000Base-T Transmit Timing-- Internal Delay .......................................... 65 Figure 18. RGMII 1000Base-T Receive Timing-- Trace Delay ............................................. 66 Figure 19. RGMII 1000Base-T Receive Timing-- Internal Delay .......................................... 67 Figure 20. MII 100Base-TX Transmit Timing ........... 68 Figure 21. MII 100Base-TX Receive Timing ............ 69 Figure 22. MII 10Base-T Transmit Timing................. 70 Figure 23. MII 10Base-T Receive Timing................. 71 Figure 24. Serial Management Interface Timing ...... 72 Figure 25 Reset Timing........................................... 73 Figure 26. Clock Timing ........................................... 74 Figure 27. JTAG Timing ........................................... 75
Agere Systems Inc.
3
TruePHY ET1011 Gigabit Ethernet Transceiver
Preliminary Data Sheet April 2004
Functional Description
Agere Systems ET1011 is a gigabit Ethernet transceiver that simultaneously transmits and receives on each of the four UTP pairs of category 5 cable (signal dimensions or channels A, B, C, and D) at 125 Msymbols/s using fivelevel pulse amplitude modulation (PAM). Figure 1 is a block diagram of its basic configuration.
GTX_CLK TX_CLK TXD[7:0] TX_ER TX_EN
PMA D PMA C PMA B
PMA A RGMII GMII MII RTBI TBI BLW Correction Gain Control Bias PCS NEXT Cancellers Echo Canceller Transmit Shaping DAC Hybrid
TRD[0-3]
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RX_CLK RXD[7:0] RX_ER RX_DV COL CRS
FFE
ADC
PGA
RSET
Trellis Decoder
Timing Control AutoNegotiation
Clock Generator
LEDS Config PHYAD[4:0] MDC MDIO MDINT_N
LEDS/ Config
JTAG/ Test
10BASE-T
Management Interface
Clock MI Registers Reset
TCK TRST_N TMS TDI TDO SYS_CLK XTAL_1 XTAL_2 RESET_N
Figure 1. ET1011 Block Diagram
Oversampling Architecture
The ET1011 architecture uses oversampling techniques to sample at two times the symbol rate. A fractionally spaced feed forward equalizer (FFE) adapts to remove intersymbol interference (ISI) and to shape the spectrum of the received signal to maximize the (SNR) at the trellis decoder input. The FFE equalizes the channel to a fixed target response. Oversampling enables the use of a fractionally spaced equalizer (FSE) structure for the FFE, resulting in symbol rate clocking for both the FFE and the rest of the receiver. This provides robust operation and substantial power savings.
Automatic Speed Downshift
Automatic speed downshift is an enhanced feature of autonegotiation that allows the ET1011 to:
Fallback in speed, based on cabling conditions or link partner abilities. Operate over CAT-3 cabling (in 10Base-T mode). Operate over two-pair CAT-5 cabling (in 100Base-TX mode).

For speed fallback, the ET1011 first tries to autonegotiate by advertising 1000Base-T capability. After a number of failed attempts to bring up the link, the ET1011 falls back to advertising 100Base-TX and restarts the autonegotiation process. This process continues through all speeds down to 10Base-T. At this point, there are no lower speeds to try and so the host enables all technologies and starts again. PHY configuration register, address 22, bits 11and 10 enable automatic speed downshift and specifies if fallback to 10Base-T is allowed. PHY control register, address 23, bits 11and 12 specify the number of failed attempts before downshift (programmable to 1, 2, 3, or 4 attempts).
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Agere Systems Inc.
Preliminary Data Sheet April 2004
TruePHY ET1011 Gigabit Ethernet Transceiver
Hybrid The hybrid subtracts the transmitted signal from the input signal allowing full-duplex operation on each of the twisted-pair cables. Programmable Gain Amplifier (PGA) The PGA operates on the received signal in the analog domain prior to the analog-to-digital converter (ADC). The gain control module monitors the signal at the output of the ADC in the digital domain to control the PGA. It implements a gain that maximizes the signal at the ADC while ensuring that no hard clipping occurs. Clock Generator A clock generator circuit uses the 25 MHz input clock signal and a phase-locked loop (PLL) circuit to generate all the required internal analog and digital clocks. A 125 MHz system clock is also generated and is available as an output clock. Analog-to-Digital Converter The ADC operates at 250 MHz oversampling at twice the symbol rate in 1000Base-T and 100Base-TX. This enables innovative timing recovery and fractional skew correction and has allowed transfer of analog complexity to the digital domain. Timing Recovery/Generation The timing recovery and generator block creates transmit and receive clocks for all modes of operation. In transmit mode, the 10Base-T and 100Base-TX modes use the 25 MHz clock input. While in receive mode, the input clock is locked to the receive data stream. 1000Base-T is implemented using a master-slave timing scheme, where the master transmit and receive are locked to the 25 MHz clock input, and the slave acquires timing information from the receive data stream. Timing recovery is accomplished by first acquiring lock on one channel and then making use of the constant phase relationship between channels to lock on the other pairs, resulting in a simplified PLL architecture. Timing shifts due to changing environmental conditions are tracked by the ET1011.
Functional Description (continued)
Transmit Functions
1000Base-T Encoder In 1000Base-T mode, the ET1011 translates 8-bit data from the MAC interfaces into a code group of four quinary symbols that are then transmitted by the PMA as 4D five-level PAM signals over the four pairs of CAT-5 cable. 100Base-TX Encoder
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In 100Base-TX mode, 4-bit data from the media independent interface (MII) is 4B/5B encoded to output 5-bit serial data at 125 MHz. The bit stream is sent to a scrambler, and then encoded to a three-level MLT3 sequence that is then transmitted by the PMA. 10Base-T Encoder In 10Base-T mode, the ET1011 transmits and receives Manchester-encoded data.
Receive Functions
Decoder 1000Base-T In 1000Base-T mode, the PMA recovers the 4D PAM signals after compensating for the cabling conditions. The resulting code group is decoded to 8-bit data. Data stream delimiters are translated appropriately, and the data is output to the receive data pins of the MAC interfaces. The GMII receive error signal is asserted when invalid code groups are detected in the data stream. Decoder 100Base-TX In 100Base-TX mode, the PMA recovers the threelevel MLT3 sequence that is descrambled and 5B/4B decoded to 4-bit data. This is output to the MII receive data pins after data stream delimiters have been translated appropriately. The MII receive error signal is asserted when invalid code groups are detected in the data stream. Decoder 10Base-T In 10Base-T mode, the ET1011 decodes the Manchester-encoded received signal.
Agere Systems Inc.
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TruePHY ET1011 Gigabit Ethernet Transceiver
Preliminary Data Sheet April 2004
Automatic MDI Crossover During autonegotiation, the ET1011 automatically detects and sets the required MDI configuration so that the remote transmitter is connected to the local receiver and vice versa. This eliminates the need for crossover cables or crosswired (MDIX) ports. If the remote device also implements automatic MDI crossover, and/or the crossover is implemented in the cable, the crossover algorithm ensures that only one element implements the required crossover. Polarity Inversion Correction In addition to automatic MDI crossover that is necessary for autonegotiation, 10Base-T, and 100Base-TX operation, the ET1011 automatically corrects crossover of the additional two pairs used in 1000Base-T. Polarity inversion on all pairs is also corrected. Both of these effects may arise if the cabling has been incorrectly wired.
Functional Description (continued)
Adaptive Fractionally Spaced Equalizer The ET1011's unique oversampling architecture employs an FSE in place of the traditional FFE structure. This results in robust equalization of the communications channel, which translates to superior bit error rate (BER) performance over the widest variety of worst-case cabling scenarios. The all-digital equalizer automatically adapts to changing conditions.
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Echo and Crosstalk Cancellers Since the four twisted pairs are bundled together and not insulated from each other in Gigabit Ethernet, each of the transmitted signals is coupled onto the three other cables and is seen at the receiver as near-end crosstalk (NEXT). A hybrid circuit is used to transmit and receive simultaneously on each pair. If the transmitter is not perfectly matched to the line, a signal component will be reflected back as an echo. Reflections can also occur at other connectors or cable imperfections. The ET1011 cancels echo and NEXT by subtracting an estimate of these signals from the equalizer output. Baseline Wander Correction A known issue for 1000Base-T and 100Base-TX is that the transformer attenuates at low frequencies. As a result, when a large number of symbols of the same sign are transmitted consecutively, the signal at the receiver gradually dies away. This effect is called baseline wander. By employing a circuit that continuously monitors and compensates for this effect, the probability of encountering a receive symbol error is reduced.
Carrier Sense (128-pin TQFP only)
The carrier sense signal (CRS) of the MAC interface is asserted by the ET1011 whenever the receive medium is nonidle. In half-duplex mode, CRS may also be asserted when the transmit medium is nonidle. The CRS may be enabled on transmit in half-duplex mode by writing to the PHY configuration register, address 22, bit 15.
Autonegotiation
Autonegotiation is implemented in accordance with IEEE 802.3. The device supports 10Base-T, 100BaseTX, and 1000Base-T and can autonegotiate between them in either half- or full-duplex mode. It can also parallel detect 10Base-T or 100Base-TX. If autonegotiation is disabled, a 10Base-T or 100Base-TX link can be manually selected via the IEEE MII registers. Pair Skew Correction In gigabit Ethernet, pair skew (timing differences between pairs of cable) can result from differences in length or manufacturing variations between the four individual twisted-pair cables. The ET1011 automatically corrects for both integer and fractional symbol timing differences between pairs. 6
Agere Systems Inc.
Preliminary Data Sheet April 2004
TruePHY ET1011 Gigabit Ethernet Transceiver
100Base-TX In 100Base-TX mode, the ET1011 monitors the link and determines the link quality based on signal energy, mean square error and scrambler lock. If the link quality is deemed insufficient, transmit and receive data are disabled. If the link had been autonegotiated then control is handed back to autonegotiation. If the link had been manually set, the 100Base-TX receiver is retrained, and the transmitter is set to transmit idle. Once the link quality has been recovered, data transmit and receive are enabled. 10Base-T In 10Base-T mode, the ET1011 monitors the link and determines the link quality based on the presence of valid link pulses. If the link is deemed to have failed and the link had been autonegotiated, then control is handed back to autonegotiation. If the link had been manually set, the ET1011 continues to try to reestablish the link.
Functional Description (continued)
Link Monitor
1000Base-T Once 1000Base-T is autonegotiated and the link is established, both link partners continuously monitor their local receiver status. If the master device determines a problem with its receiver, it signals the slave and both devices cease transmitting data but transmit IDLE. If the master retrains its receiver within 750 ms, then normal operation recommences. Otherwise, both www..com devices restart autonegotiation. If the slave device determines a problem with its receiver, it ceases transmitting and expects the master to transmit the IDLE sequence. If the slave retrains its receiver within 350 ms, normal operation recommences when the master signals that its receiver is ready. If either receiver fails to reacquire, then autonegotiation is restarted.
Agere Systems Inc.
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TruePHY ET1011 Gigabit Ethernet Transceiver
Preliminary Data Sheet April 2004
Functional Description (continued)
Loopback Mode
Enabling loopback mode allows in-circuit testing of the ET1011's digital and analog data path. The ET1011 provides several options for loopback that test and verify various functional blocks within the PHY. These are digital loopback and analog loopback. Figure 2 is a block diagram that shows the PHY loopback functionality.
Digital Loopback
Replica Loopback
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MAC / Switch
G M I I
PHY Digital
PHY AFE
Remote PHY
Analog Loopback
Figure 2. Loopback Functionality The loopback mode is selected by setting the respective bit in the PHY loopback control register (MII register address 19, bits 9:15). The default loopback mode is digital MII loopback. Loopback is enabled by writing to the PHY control register, address 0, bit 14.
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Agere Systems Inc.
Preliminary Data Sheet April 2004
TruePHY ET1011 Gigabit Ethernet Transceiver
Functional Description (continued)
Digital Loopback
Digital loopback provides the ability to loop the transmitted data back to the receiver at various internal points between the MAC interface and the analog front end (AFE) circuitry. The point at which the data is looped back is selected using the loopback control register (address 19) with the following options being available: MII, PCS, PMD and all digital. Selecting the MII option gives a simple loopback with minimal latency where the data is looped back directly at the media-independent interface. This loopback is currently set as the default, but it should be noted that it only exercises a small percentage of the PHY circuitry. When the all digital option is selected, the transmitted data is looped back at the interface between the digital and the analog circuitry. thereby exercising a high percentage of the digital logic. The PCS and PMD options represent intermediate points between the two extremes. Figure 3 shows a block diagram of digital loopback. www..com
PHY Digital MAC / Switch G M I I
GMII PCS PMA
PHY AFE
Figure 3. Digital Loopback
Agere Systems Inc.
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TruePHY ET1011 Gigabit Ethernet Transceiver
Preliminary Data Sheet April 2004
Functional Description (continued)
Analog Loopback
Analog loopback provides the ability to loop the transmitted signal back to the receiver within the AFE. The point at which the signal is looped back is selected using the loopback control register with the following options being provided: replica and line driver. Selecting the replica option causes the transmitted signal to be looped back through the replica generation circuitry of the on-chip hybrid, thereby allowing most of the digital and analog circuitry to be exercised. This loopback mode may be used even when the device is connected to a network because nothing is transmitted to or received from the MDI in this case. The most thorough www..com loopback test available without the cooperation of a link partner is provided by selecting the line driver option where the PHY transmits to and receives from the MDI. However, in general, this loopback may not be used when the device is connected to a network because it could cause an unanticipated response from the link partner. Figure 4 shows a block diagram of replica analog loopback and Figure 5 shows a block diagram of line driver analog loopback.
MAC / Switch
G M I I
PHY Digital
PHY AFE
Figure 4. Replica Analog Loopback
MAC / Switch
G M I I
PHY Digital
PHY AFE
RJ-45
Figure 5. Line Driver Analog Loopback
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Agere Systems Inc.
Preliminary Data Sheet April 2004
TruePHY ET1011 Gigabit Ethernet Transceiver
Software Powerdown Mode Software powerdown is entered when bit 11 of the control register (MII register address 0 bit 11) is set. In software powerdown, all PHY functions except the serial management interface and clock circuitry are disabled. The MII registers can be read or written. If the system clock output is enabled (MII register address 22 bit 4), the 125 MHz system clock will still be available for use by the MAC on pin SYS_CLK. At exit from software powerdown, the ET1011 does the following:
Functional Description (continued)
LEDs
Seven status LEDs are provided. These can be used to indicate speed of operation, duplex mode, link status, etc. There is a very high degree of programmability allowed. Hence, the LEDs can be programmed to different status functions from their default value, or they can be controlled directly from the MII register interface. The LED signal pins can also be used for general-purpose I/O if not needed for LED indication.
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The 68-pin MLCC has only two LEDs. Both can be programmed through MII register 28 to provide all speed indications as well as link and activity indications.
Initializes all digital logic and state machines.
Resetting the ET1011
The ET1011 provides the ability to reset the device by hardware (pin RESET_N) or via software through the management interface. A hardware reset is accomplished by driving the active-low pin RESET_N to 0 volts for a minimum of 1 s. The configuration pins and the physical address configuration are read during a hardware reset. A software reset is accomplished by setting bit 15 of the control register (MII register address 0 bit 15). The configuration pins and the physical address configuration are not read during software reset.
Note: At exit from software powerdown, the H/W configuration pins and the PHY address pins are not reread and the MII registers are not reset to their default values. These operations are only done during reset or recovery from hardware powerdown. Wake-On-LAN Powerdown Mode ACPI power consumption compliant Wake-On-LAN mode is implemented on the ET1011 by using the IEEE standard MII registers to put the PHY into 10Base-T or 100Base-TX modes. Clearing the advertisement of 1000Base-T (MII register address 9 bits 8, 9) and setting the desired 10Base-T and 100Base-TX advertisement (MII register address 4 bits 5-8) activates this feature. This must be followed by an autonegotiation restart via the control register (MII register address 0 bit 9). Low-Power Energy-Detect Mode When COMA is asserted, low-power energy-detect (LPED) mode is enabled if LPED_EN_N is low. In this mode, the PHY monitors the cable for energy. If energy is detected, the MDINT_N pin is asserted. The PHY exits from LPED mode when COMA is deasserted. .
Low-Power Modes
The ET1011 supports a number of powerdown modes. Hardware Powerdown Mode Hardware powerdown is entered when the COMA signal is driven high. In hardware powerdown, all PHY functions (analog and digital) are disabled. During hardware powerdown, SYS_CLK is not available and the MII registers are not accessible. At exit from hardware powerdown, the ET1011 does the following:

Initializes all analog circuits including the PLL. Initializes all digital logic and state machines. Reads and latches the PHY address pins. Initializes all MII registers to their default values (H/W configuration pins are reread). 11
Agere Systems Inc.
TruePHY ET1011 Gigabit Ethernet Transceiver
Preliminary Data Sheet April 2004
Pin Information
Pin Diagram, 128-Pin TQFP
TXD[2] TXD[1] TXD[0] TX_CTL/TX_EN/TXD[8] TX_ER/TXD[9] DVSS NC TXC/GTX_CLK/PMA_TX_CLK DVSS DVDDIO TX_CLK DVSS CRS/COMMA COL/PMA_RX_CLK1 NC RXC/RX_CLK/PMA_RX_CLK[0] DVSS DVDDIO RX_ER/RXD[9] RX_CTL/RX_DV/RXD[8] RXD[0] RXD[1] RXD[2] RXD[3] DVDDIO DVSS
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128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
VDD DVSS TXD[3] TXD[4] TXD[5] TXD[6] TXD[7] DVSS DVDDIO TCK VDD DVSS DVSS TRST_N TMS/SYS_CLK_EN_N TDI/LPED_EN_N TDO MAC_IF_SEL[0] MAC_IF_SEL[1] MAC_IF_SEL[2] AUTO_MDI_EN VDD DVSS NC COMA VDD DVSS AVDDL AVSS AVDDH CLK_IN/XTAL_1 XTAL_2 AVSS RESET_N NC NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
AGERE SYSTEMS ET1011
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
VDD DVSS RXD[4] RXD[5] RXD[6] RXD[7] DVDDIO DVSS SYS_CLK DVSS VDD MDC MDIO MDINT_N DVDDIO PRES LED_COL/MAS_CFG LED_LNK/PAUSE LED_10/SPEED_10 LED_100/SPEED_100 LED_1000/SPEED_1000 VDD DVSS CTRL_1V0 CTRL_2V5 DVDDIO DVSS LED_DUP/DUPLEX LED_ACT/MDIX_SEL VDD DVSS PHYAD[0] PHYAD[1] PHYAD[2] PHYAD[3] PHYAD[4] NC NC
Figure 6. Pin Diagram for ET1011 in 128-Pin TQFP Package (Top View)
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TRD[0]+ AVSS TRD[0]- AVSS AVDDL NC TRD[1]+ AVSS TRD[1]- AVSS AVDDL AVSS AVDDH RSET AVDDL TRD[2]+ AVSS TRD[2]- AVSS AVDDL NC TRD[3]+ AVSS TRD[3]- AVSS AVDDL
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Agere Systems Inc.
Preliminary Data Sheet April 2004
TruePHY ET1011 Gigabit Ethernet Transceiver
Pin Information (continued)
Pin Diagram, 68-Pin MLCC
TX_CTL/TXD[4] RX_CTL/RXD[4]
DVDDIO
DVDDIO
TXD[3]
TXD[2]
TXD[1]
TXD[0]
DVDDIO 53
TX_CLK
RXD[0]
RXD[1]
RXD[2]
RXD[3] 54
68
67
66
65
64
63
TXC
62
61
60
59
58
57
56
55
DVDDIO TCK DVDD DVSS TRST_N TMS/SYS_CLK_EN_N TDI/LPED_EN_N TDO MAC_IF_SEL0 MAC_IF_SEL1 DVDD COMA DVDD AVDDL AVDDH XTAL_1/CLK_IN XTAL_2
52
DVDD
RXC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
*
51 50 49 48 47 46 45
DVDDIO SYS_CLK DVDD MDC MDIO MDINT_N DVDDIO PRES LED_LNK/PAUSE LED_1000 DVDD CTRL_1V0 CTRL_2V5 DVDDIO PHYAD[0] PHYAD[1] PHYAD[2]
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AGERE SYSTEMS ET1011
44 43 42 41 40 39 38 37 36 35 33 AVDDL 32 TRD[3]- 34 PHYAD[3]
EXPOSED PAD (DVSS AND AVSS)
19 20 21 22 23 24 25 26 27 28 29 TRD[2]- 30 AVDDL 31 TRD[3]+
AVDDH
TRD[0]+
TRD[1]+
RSET
RESET_N
Figure 7. Pin Diagram for ET1011 in 68-Pin MLCC Package (Top View)
Agere Systems Inc.
TRD[2]+
TRD[0]-
TRD[1]-
AVDDL
AVDDL
AVDDL
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TruePHY ET1011 Gigabit Ethernet Transceiver
Preliminary Data Sheet April 2004
Pin Information (continued)
Pin Descriptions, 128-Pin TQFP and 68-Pin MLCC
Table 1. Agere Systems ET1011 Device Signals by Interface, 128-Pin TQFP and 68-Pin MLCC Name Description Pad Type Hyst./ OpenDrain H H H H -- -- -- -- Internal 3-State Analog Pull-Up/ Pull-Down -- -- -- -- -- -- -- -- -- -- -- -- Z Z Z Z -- -- -- -- -- -- -- -- Pin # 128-TQFP Pin # 68-MLCC
MAC: GMII--Gigabit Media Independent Interface (128-pin TQFP only) GTX_CLK TX_ER www..com TX_EN TXD[7:0] RX_CLK RX_ER RX_DV RXD[7:0] GMII transmit clock Transmit error Transmit enable Transmit data bits Receive clock Receive error Receive data valid Receive data bits I I I I O O O O 121 124 125 126, 127, 128, 3, 4, 5, 6, 7 113 110 109 108, 107, 106, 105, 100, 99, 98, 97 116 115 121 126, 127, 128, 3 125 113 108, 107, 106, 105 109 118 124 125 126, 127, 128, 3 113 110 109 108, 107, 106, 105 116 115 -- -- -- -- -- -- -- --
CRS COL TXC TXD[3:0] TX_CTL RXC RXD[3:0] RX_CTL TX_CLK TX_ER TX_EN TXD[3:0] RX_CLK RX_ER RX_DV RXD[3:0] CRS COL
Carrier sense Collision detect RGMII transmit clock Transmit data bits Transmit control Receive clock Receive data bits Receive control MII transmit clock Transmit error Transmit enable Transmit data bits Receive clock Receive error Receive data valid Receive data bits Carrier sense Collision detect
O O I I I O O O O I I I O O O O O O
-- -- H H H -- -- -- -- H H H -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Z Z -- -- -- Z Z Z Z -- -- -- Z Z Z Z Z Z
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- 63 68, 67, 66, 65 64 60 54, 55, 56, 57 58 -- -- -- -- -- -- -- -- -- --
MAC: RGMII--Reduced Gigabit Media Independent Interface
MAC: MII--Media Independent Interface (128-pin TQFP only)
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Agere Systems Inc.
Preliminary Data Sheet April 2004
TruePHY ET1011 Gigabit Ethernet Transceiver
Pin Information (continued)
Pin Descriptions, 128-Pin TQFP and 68-Pin MLCC (continued)
Table 1. Agere Systems ET1011 Device Signals by Interface, 128-Pin TQFP and 68-Pin MLCC (continued) Name Description Pad Hyst./ Internal 3-State Analog Type Open- Pull-Up/ Drain Pull-Down I I H H -- -- -- -- -- -- Pin # 128-TQFP Pin # 68-MLCC
MAC: TBI--Ten-Bit Interface (128-pin TQFP only) PMA_ TX_CLK TXD[9:0] www..com TBI transmit clock Transmit data bits 121 126, 127, 128, 3, 4, 5, 6, 7, 125, 124 113 108, 107, 106, 105, 100, 99, 98, 97, 109, 110 115 116 121 4, 3, 128, 127, 126 -- --
PMA_RX_CLK[0] TBI receive clock RXD[9:0] Receive data bits
O O
-- --
-- --
Z Z
-- --
-- --
PMA_RX_ CLK[1] TBI receive clock COMMA Valid comma detect MAC: RTBI--Reduced Ten-Bit Interface TXC TXD[4:0] RTBI transmit clock Transmit data bits
O I I I
-- H H H
-- -- -- --
Z -- -- --
-- -- -- --
-- --
RXC RXD[4:0]
RTBI receive clock Receive data bits
O O
-- --
-- --
Z Z
-- --
63 68, 67, 66, 65 64 113 60 108, 107, 58, 54, 55, 106, 105, 109 56, 57 39 41 45 47 54 56 60 62 52 19 20 22 23 28 29 31 32 26
MDI: Transformer Interface TRD[0]+ TRD[0]- TRD[1]+ TRD[1]- TRD[2]+ TRD[2]- TRD[3]+ TRD[3]- RSET Transmit and receive differential pair Transmit and receive differential pair Transmit and receive differential pair Transmit and receive differential pair Analog reference resistor I/O I/O I/O I/O I/O -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- A A A A A
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TruePHY ET1011 Gigabit Ethernet Transceiver
Preliminary Data Sheet April 2004
Pin Information (continued)
Pin Descriptions, 128-Pin TQFP and 68-Pin MLCC (continued)
Table 1. Agere Systems ET1011 Device Signals by Interface, 128-Pin TQFP and 68-Pin MLCC (continued) Name Description Pad Hyst./ Type OpenDrain I I I I/O O -- -- -- -- OD Internal 3-State Analog Pull-Up/ Pull-Down Pull-down Pull-up Pull-down Pull-up -- -- -- -- -- -- -- -- -- -- -- Pin # 128TQFP 70, 71, 69, 68, 67 91 90 89 Pin # 68MLCC 34, 35, 36, 37 PHYAD [3:0] 48 47 46
Management Interface PHYAD[4:0]
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PHY address 4--1 PHY address 0 Management interface clock Management data I/O Management interface interrupt 1000Base-T speed select 100Base-TX speed select 10Base-T speed select Half- or full-duplex configuration Auto-MDI detection enable MDI/MDI-X autodetection Master slave configuration Pause mode MAC interface select 1 MAC interface select 2 System clock enable Low power energy detection enable Precision resistor
MDC MDIO MDINT_N Configuration1 SPEED_1000 SPEED_100 SPEED_10 DUPLEX AUTO_MDI_EN MDIX_SEL MAS_CFG PAUSE MAC_IF_SEL[1] MAC_IF_SEL[2] SYS_CLK_EN_N LPED_EN_N PRES
I I I I I I I I I I I I I
-- -- -- -- -- -- -- -- -- -- -- -- --
Pull-up Pull-up Pull-up Pull-up Pull-up Pull-down Pull-down Pull-down Pull-down Pull-down Pull-up Pull-up --
-- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- --
82 83 84 75 21 74 86 85 19 20 15 16 87
-- -- -- -- -- -- -- 43 10 -- 6 7 44
1. Configuration signals are multiplexed with the LED controls. During a reset, the status of the configuration pins are latched and used to set the configuration and later to select the polarity to drive the LEDs.
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Agere Systems Inc.
Preliminary Data Sheet April 2004
TruePHY ET1011 Gigabit Ethernet Transceiver
Pin Information (continued)
Pin Descriptions, 128-Pin TQFP and 68-Pin MLCC (continued)
Table 1. Agere Systems ET1011 Device Signals by Interface, 128-Pin TQFP and 68-Pin MLCC (continued) Name Description Pad Type Hyst./ OpenDrain -- -- -- -- -- -- -- Internal 3-State Analog Pin # Pin # Pull-Up/ 128-TQFP 68-MLCC Pull-Down Pull-up Pull-up Pull-up Pull-up Pull-down Pull-down Pull-down -- -- -- -- -- -- -- -- -- -- -- -- -- -- 82 83 84 75 85 86 74 42 -- -- -- 43 -- --
LED Interface LED_1000 LED_100 www..com LED_10 LED_DUP LED_LNK LED_COL LED_ACT JTAG TCK TRST_N TMS TDI TDO CLK_IN XTAL_1 XTAL_2 SYS_CLK RESET_N COMA CTRL_1V0 CTRL_2V5 Test clock Test reset Test mode select Test data input Test data output Reference clock input Reference crystal input Reference crystal System clock Reset Hardware powerdown Regulator control 1.0 V Regulator control 2.5 V I I I I O I/O I/O I/O O I I O O -- H -- -- -- -- -- -- -- -- -- -- -- -- Pull-down Pull-up Pull-up Pull-up -- -- -- -- -- Pull-down -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- A A A -- -- -- A A 10 14 15 16 17 31 31 32 94 34 25 79 78 2 5 6 7 8 16 16 17 50 18 12 40 39 1000Base-T LED 100Base-TX LED 10Base-T LED Duplex LED Link established LED Collision LED Transmit and receive activity O O O O O O O
Clocking and Reset
Regulator Control
1. Configuration signals are multiplexed with the LED controls. During a reset, the status of the configuration pins are latched and used to set the configuration and later to select the polarity to drive the LEDs.
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TruePHY ET1011 Gigabit Ethernet Transceiver
Preliminary Data Sheet April 2004
Pin Information (continued)
Pin Descriptions, 128-Pin TQFP and 68-Pin MLCC (continued)
Table 1. Agere Systems ET1011 Device Signals by Interface, 128-Pin TQFP and 68-Pin MLCC (continued) Name Description Pad Type Hyst./ OpenDrain -- Internal 3-State Analog Pull-Up/ Pull-Down -- -- -- Pin # 128-TQFP Pin # 68-MLCC
Power, Ground, and No Connect DVDDIO
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Digital I/O 2.5 V or 3.3 V supply Digital core 1.0 V supply Digital ground
VDD
VDD DVSS2
VDD VSS
-- --
-- --
-- --
-- --
AVDDH AVDDL AVSS2
Analog power 2.5 V Analog power 1.0 V Analog ground
VDD VDD VSS
-- -- --
-- -- --
-- -- --
-- -- --
NC
Reserved--do not connect
--
--
--
--
--
1, 38, 45, 51, 53, 59, 62 1, 11, 22, 26, 3, 11, 13, 73, 81, 92, 102 41, 49, 52 4 2, 4, 8, 12, 13, 23, 27, 72, 76, 80, 93, 95, 101, 103, 112, 117, 120, 123 30, 51 15, 25 28, 43, 49, 14, 21, 24, 53, 58, 64 27, 30, 33 29, 33, 40, 42, -- 46, 48, 50, 55, 57, 61, 63 -- 24, 35, 36, 37, 38, 44, 59, 65, 66, 114, 122
9, 77, 88, 96, 104, 111, 119
1. Configuration signals are multiplexed with the LED controls. During a reset, the status of the configuration pins are latched and used to set the configuration and later to select the polarity to drive the LEDs. 2. For the 68-MLCC, all AVss and DVss pins share a common ground pin (pad) in the center of the device.
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Preliminary Data Sheet April 2004
TruePHY ET1011 Gigabit Ethernet Transceiver
Pin Information (continued)
Pin Descriptions, 128-Pin TQFP and 68-Pin MLCC (continued)
Table 2. Multiplexed Signals on the ET1011
Default COL CRS GTX_CLK www..com Pin # 128-TQFP 115 116 121 Pin # 68-MLCC -- -- -- Alternate COL1, 6 PMA_RX_CLK[1]2 CRS1, 6 COMMA2 GTX_CLK1 PMA_TX_CLK2 TXC3, 4 LED_ACT MDIX_SEL5 LED_COL MAS_CFG5 LED_DUP DUPLEX5 LED_LNK PAUSE5 LED_1000 SPEED_10005 LED_100 SPEED_1005 LED_10 SPEED_105 RX_CLK1, 6 PMA_RX_CLK[0]2 RXC3, 4 RX_ER1, 6 RXD[9]2 RX_DV1, 6 RXD[8]2 RX_CTL3 TDI LPED_EN_N5 TMS SYS_CLK_EN_N5 TX_ER1, 6 TXD[9]2 TX_EN1, 6 TXD[8]2 XTAL_1 CLK_IN
LED_ACT LED_COL LED_DUP LED_LNK LED_1000 LED_100 LED_10 RX_CLK
74 86 75 85 82 83 84 113
-- -- -- -- -- -- -- --
RX_ER RX_DV
110 109
-- --
TDI
16 15 124 125 31
4. RTBI signal. 5. Reset/configuration signal. 6. MII signal.
7 6 -- -- 16
TMS
TX_ER TX_EN XTAL_1
1. GMII signal. 2. TBI signal. 3. RGMII signal.
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TruePHY ET1011 Gigabit Ethernet Transceiver
Preliminary Data Sheet April 2004
Hardware Interfaces
The following hardware interfaces are included on the ET1011 gigabit Ethernet transceiver:
MAC interfaces: -- GMII (128-pin TQFP only) -- RGMII -- MII (128-pin TQFP only) -- TBI (128-pin TQFP only) -- RTBI Media dependent interface Management interface

Configuration interface LED interface Clock and reset signals JTAG interface Regulator control Power and ground signals

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Several of the pins of the MAC interface are multiplexed, but they are designed to be interchangeable so that the device can change the MAC interface once the transmission capabilities (1000Base-T, 100Base-TX, and 10BaseT) are established. The following diagram shows the various interfaces on each ET1011 and how they connect to the MAC and other support devices in a typical application.
Agere Systems ET1011 Gigabit Ethernet PHY
GTX_CLK TX_CLK TXD[7:0] TX_ER TX_EN RX_CLK RXD[7:0] RX_ER RX_DV COL CRS MAC_IF_SEL[2:0] PHYAD[4:0] MDC MDIO MDINT_N TCK TRST_N TMS TDI TDO COMA RESET_N XTAL_1 XTAL_2 LED_10 LED_100 LED_1000 LED_DUP LED_LNK LED_ACT LED_COL
MAC
ET1011
TRD[0]+/TRD[1]+/TRD[2]+/TRD[3]+/RSET
CTRL_2V5 CTRL_1V0
2.5V Power Plane
1.0V Power Plane
Figure 8. ET1011 Gigabit Ethernet Card Block Diagram
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Preliminary Data Sheet April 2004
TruePHY ET1011 Gigabit Ethernet Transceiver
Hardware Interfaces (continued)
MAC Interface
The ET1011 supports RGMII, GMII, MII, RTBI, and TBI interfaces to the MAC. The MAC interface mode is selected via the hardware configuration pins, MAC_IF_SEL[2:0]. Gigabit Media Independent Interface (GMII) (128-pin TQFP only) The GMII is fully compliant with IEEE 802.3 clause 35. The www..com GMII interface mode is selected by setting the hardware configuration pins MAC_IF_SEL[2:0] = 000.
TX_ER GTX_CLK TXD[7:0] TX_EN RX_CLK
MAC
RX_ER RX_DV RXD[7:0] CRS COL
PHY
Figure 9. GMII MAC-PHY Signals Table 3. GMII Signal Description (1000Base-T Mode) (128-pin TQFP Only) Pin Name GTX_CLK TX_ER TX_EN TXD[7:0] Pin # Pin Description 128 TQFP 121 Transmit clock Functional Description
RX_CLK RX_ER RX_DV RXD[7:0]
CRS
COL
The MAC drives this 125 MHz clock signal that is held low during autonegotiation or when operating in modes other than 1000Base-T. 124 Transmit error The MAC drives this signal high to indicate a transmit coding error. 125 Transmit enable The MAC drives this signal high to indicate that data is available on the transmit data bus. 126, 127, Transmit data The MAC transmits data synchronized with RX_CLK to the ET1011 128, 3, 4, bits 7--0 for transmission on the media dependent (transformer) interface. 5, 6, 7 113 Receive clock The ET1011 generates a 125 MHz clock to synchronize receive data. 110 Receive error The ET1011 drives RX_ER to indicate that an error was detected in the frame that was received and is being transmitted to the MAC. 109 Receive data The ET1011 drives RX_DV to indicate that it is sending recovered valid and decoded data to the MAC. The ET1011 transmits data that is synchronized with RX_CLK to the 108, 107, Receive data MAC. 106, 105, 100, 99, 98, 97 116 Carrier sense The carrier sense signal (CRS) of the MAC interface is asserted by the ET1011 whenever the receive medium is nonidle. In half-duplex mode, CRS may also be asserted when the transmit medium is nonidle. The CRS may be enabled on transmit in half-duplex mode by writing to the PHY configuration register, address 22, bit 15. 115 Collision detect In 10Base-T, 100Base-TX, and 1000Base-T half-duplex modes, COL is asserted when both transmit and receive media are nonidle.
Agere Systems Inc.
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TruePHY ET1011 Gigabit Ethernet Transceiver
Preliminary Data Sheet April 2004
Hardware Interfaces (continued)
TXC
Reduced Gigabit Media Independent Interface (RGMII) The RGMII interface is fully compliant with the RGMII Rev. 1.3 specification. The RGMII interface mode is selected by setting the hardware configuration pins MAC_IF_SEL[2:0] = 100 (trace delay) or 110 (DLL delay).
TXD[3:0]
TX_CTL MAC RXC PHY
RXD[3:0]
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RX_CTL
Figure 10. RGMII MAC-PHY Signals Table 4. RGMII Signal Description (1000Base-T Mode) Pin Name TXC Pin # Pin # Pin Description 128-TQFP 68-MLCC 121 63 Transmit clock Functional Description
TXD[3:0]
126, 127, 128, 3 125
68, 67, 66, 65 64
TX_CTL
RXC
113
60
RXD[3:0]
108, 107, 106, 105, 109
54, 55, 56, 57 58
RX_CTL
The MAC drives this 125 MHz clock signal that is held low during autonegotiation or when operating in modes other than 1000Base-T. To obtain the 1 gigabit transmission rate, the MAC uses both the positive and negative clock transitions. Transmit data The MAC transmits data synchronized with RX_CLK to the bits ET1011 for transmission on the media dependent (transformer) interface. The MAC sends data in two 4-bit nibbles. Transmit control The MAC transmits control signals across this line (TX_ER and TX_EN). The MAC transmits TX_EN1 on a positive transition of TXC and TX_EN and TX_ER1 on the negative transition of TXC. Receive clock The ET1011 generates a 125 MHz clock to synchronize receive data. To obtain the 1 gigabit transmission rate, the ET1011 uses both the positive and negative clock transitions. Receive data The ET1011 transmits data that is synchronized with RX_CLK to the MAC. The ET1011 sends data in two 4-bit nibbles. Receive control The ET1011 transmits control signals across this line (RX_ER and RX_EN). The ET1011 transmits RX_DV1 on a positive transition of RXC and RX_EN1 and RX_ER1 on the negative transition of TXC.
1. Reference the GMII interface for description of the following parameters: TX_EN, TX_ER, RX_DV, RX_EN, and RX_ER.
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Preliminary Data Sheet April 2004
TruePHY ET1011 Gigabit Ethernet Transceiver
25 MHz at the GTX_CLK pin. The ET1011 then uses a FIFO to resynchronize data presented synchronously with this reference clock.
TX_CLK TX_ER TX_EN TXD[3:0] RX_CLK
Hardware Interfaces (continued)
Media Independent Interface (MII) (128-pin TQFP only) The MII is fully compliant with IEEE 802.3 clause 22. The MII interface mode is selected by setting the hardware configuration pins MAC_IF_SEL[2:0] = 000. In 100Base-TX and 10Base-T mode, the RXD[7:4] pins are driven low by the ET1011 and the TXD[7:4] pins are ignored. They should not be left floating but should be set either high or low. In the MII interface mode, the GTX_CLK pin may be held low. www..com An alternative to the standard MII is provided when operating in 10Base-T or 100Base-TX mode by setting hardware configuration pins MAC_IF_SEL[2:0] = 010. In this alternative interface, the MAC provides a reference clock at 2.5 MHz or
MAC
RX_ER RX_DV RXD[3:0] CRS COL
PHY
Figure 11. MII Signals
Table 5. MII Interface (100Base-TX and 10Base-T) (128-pin TQFP Only) Pin Name TX_CLK Pin # 128 TQFP 118 Pin Description Functional Description
GTX_CLK
TX_ER TX_EN TXD[3:0] RX_CLK RX_ER RX_DV RXD[3:0] CRS
COL
Transmit clock In 100Base-TX mode, the ET1011 generates 25 MHz reference clocks and in 10Base-T mode provides 2.5 MHz reference clocks. MAC_IF_SEL[2:0] = 000--this is default behavior. 121 Alternate In 100Base-TX mode, the MAC generates the 25 MHz reference clock transmit clock and in 10Base-T mode provides a 2.5 MHz reference clock. MAC_IF_SEL[2:0] = 010. 124 Transmit error The MAC drives this signal high to indicate a transmit coding error. 125 Transmit The MAC drives this signal high to indicate that data is available on enable the transmit data bus. 126, 127, Transmit data The MAC transmits data synchronized with TX_CLK to the ET1011 for 128, 3 bits transmission on the media dependent (transformer) interface. 113 Receive clock In 100Base-TX mode, the ET1011 generates 25 MHz reference clocks and in 10Base-T mode provides 2.5 MHz reference clocks. 110 Receive error The ET1011 drives RX_ER to indicate that an error was detected in the frame that was received and is being transmitted to the MAC. 109 Receive data The ET1011 drives RX_DV to indicate that it is sending recovered and valid decoded data to the MAC. 108, 107, Receive data The ET1011 transmits data synchronized with RX_CLK to the MAC. 106, 105 bits 116 Carrier sense The carrier sense signal (CRS) of the MAC interface is asserted by the ET1011 whenever the receive medium is nonidle. In half-duplex mode, CRS may also be asserted when the transmit medium is nonidle. The CRS may be enabled on transmit in half-duplex mode by writing to the PHY configuration register, address 22, bit 15. 115 Collision In 10Base-T, 100Base-TX, and 1000Base-T half-duplex modes, COL detect is asserted when both transmit and receive media are nonidle.
Agere Systems Inc.
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TruePHY ET1011 Gigabit Ethernet Transceiver
Preliminary Data Sheet April 2004
Hardware Interfaces (continued)
Ten-Bit Interface (TBI) (128-pin TQFP only) The TBI is fully compliant with IEEE 802.3 clause 36. It may be used as an alternative to the GMII in 1000Base-T mode. The TBI mode is selected by setting the hardware configuration pins MAC_IF_SEL[2:0] = 001.
PMA_TX_CLK TXD[9] TXD[8] TXD[7:0] PMA_RX_CLK
GTX-CLK TX_ER TX_EN TXD[7:0] RX_CLK
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MAC
PHY
RXD[9] RXD[8] RXD[7:0] PMA_RX_CLK[1]
RX_ER RX_DV RXD[7:0] COL
Figure 12. Ten-Bit Interface Table 6. Ten-Bit Interface (1000Base-T) (128-pin TQFP Only) Pin Name PMA_TX _CLK Pin # 128 TQFP 121 Pin Description TBI transmit clock Functional Description The MAC drives this 125 MHz clock signal and should be held low during autonegotiation or when operating in modes other than 1000Base-T. The MAC transmits data synchronized with PMA_TX_CLK to the ET1011 for transmission on the media dependent (transformer) interface. The ET1011 generates a 62.5 MHz clock to synchronize receive data for the odd code group. This signal is 180 degrees out of phase from PMA_RX_CLK[1]. The ET1011 transmits data that is synchronized with PMA_ RX_CLK[0] to the MAC.
126, 127, Transmit data bits 128, 3, 4, 5, 6, 7, 125, 124 PMA_RX _CLK[0] 113 Receive clock TXD[9:0]
108, 107, Receive data bits 106, 105, 100, 99, 98, 97, 109, 110 PMA_RX _CLK[1] 115 Receive clock RXD[9:0]
The ET1011 generates a 62.5 MHz clock to synchronize receive data for the even code group. This signal is 180 degrees out of phase from PMA_RX_CLK[0].
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Agere Systems Inc.
Preliminary Data Sheet April 2004
TruePHY ET1011 Gigabit Ethernet Transceiver
Hardware Interfaces (continued)
Reduced Ten-Bit Interface (RTBI) The RTBI is fully compliant with RGMII rev 1.3 specification. The RTBI mode is selected by setting the hardware configuration pins MAC_IF_SEL[2:0] = 101 (trace delay) or 111 (DLL delay).
TXC
TXD[4:0]
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MAC RXC PHY
RXD[4:0]
Figure 13. Reduced Ten-Bit Interface Table 7. RTBI Signal Description (1000Base-T Mode) Pin Name TXC Pin # 128-TQFP 121 Pin # 68-MLCC 63 Pin Description Transmit clock Functional Description The MAC drives this 125 MHz clock signal that is held low during autonegotiation or when operating in modes other than 1000Base-T. The MAC transmits data synchronized with TXC to the ET1011 for transmission on the media dependent (transformer) interface. The ET1011 generates a 125 MHz clock to synchronize receive data. The ET1011 transmits data that is synchronized with RXC to the MAC.
TXD[4:0]
4, 3, 128, 127, 126 113 108, 107, 106, 105, 109
68, 67, 66, Transmit data 65, 64 bits 60 Receive clock
RXC RXD[4:0]
54, 55, 56, Receive data 57, 58
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TruePHY ET1011 Gigabit Ethernet Transceiver
Preliminary Data Sheet April 2004
Hardware Interfaces (continued)
Management Interface
Serial Management Interface The MII management interface (MI) provides a simple, two-wire serial interface between the MAC and the PHY to allow access to control and status information in the internal registers of the ET1011. The interface is compliant with IEEE 802.3 clause 22 and is compatible with the clause 45.3, enabling the two systems to co-exist on the same MDIO bus. Management Frame Structure
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Frames transmitted on the MI have the following structure. Table 8. Management Frame Structure PRE Read Write
ST 01 01
OP 10 01
PHYAD aaaaa aaaaa
REGAD rrrrr rrrrr ZO 10
TA
DATA d...d d...d Z Z
IDLE
1...1 1...1
PRE (preamble): At the beginning of each transaction, the MAC may send a sequence of 32 contiguous logic one bits on MDIO with 32 corresponding cycles on MDC to provide the PHY with a pattern that it can use to establish synchronization. The ET1011 supports MF preamble suppression, and thus the MAC may initiate management frames with the ST (start of frame) pattern. ST (start of frame): The start of frame is indicated by a <01> pattern. This pattern ensures transitions from the default logic one line state to zero and back to one. When a clause 45 start of frame <00> is received, the frame is ignored OP (operation code): The operation code for a read transaction is <10>, while the operation code for a write transaction is <01>. PHYAD (phy address): The PHY address is 5 bits. The first PHY address bit transmitted and received is the MSB of the address. Only the PHY that is addressed will respond to the MI operation. REGAD (register address): The register address is 5 bits. The first register address bit transmitted and received is the MSB of the address. TA (turnaround): The turnaround time is a 2-bit time spacing between the register address field and the data field of a management frame to avoid contention during a read transaction. For a read transaction, the PHY remains in a high-impedance state for the first bit time of the turnaround and drives a zero bit during the second bit time of the turnaround. During a write transaction, the PHY expects a one for the first bit time of the turnaround and a zero for the second bit time of the turnaround. DATA (data): The data field is 16 bits. The first data bit transmitted and received is the MSB of the register being addressed. IDLE (idle condition): The IDLE condition on MDIO is a high-impedance state, and the ET1011 internal pull-up resistor will pull the MDIO line to logic one.

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Agere Systems Inc.
Preliminary Data Sheet April 2004
TruePHY ET1011 Gigabit Ethernet Transceiver
Hardware Interfaces (continued)
Table 9. Management Interface Pin Name PHYAD [4:0] Pin # 128-TQFP 71, 70, 69, 68, 67 Pin # 68-MLCC 34, 35, 36, 37 (PHYAD [3:0]) Pin Description Functional Description
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MDC
91
48
MDIO
90
47
PHY Address The physical address of the ET1011 is configured at reset by the current state of the PHYAD[4:0] pins. Once these pins have been latched in at reset, the ET1011 is accessible via the management interface at the configured address. The default address is set to 1 by internal pull up/downs. These may be overridden by external pull-up/downs. The valid range is 0 to 311. Management The management data clock (MDC) is a reference for Interface the data signal and is generated by the MAC. It should Clock be turned off when the MI is not being used. This pin has an internal pull-down resistor. MDC is nominally 2.5 MHz, and can work up to a maximum of 12.5 MHz. Management The management data input/output (MDIO) is a bidirecData I/O tional data signal between the MAC and one or more PHYs. MDIO is a 3-state pin that allows either the MAC or the selected PHY to drive this signal. This pin has an internal pull-up resistor. An external pull-up resistor should also be used, the exact value depending on the number of PHYs sharing the MDIO signal. Data signals written by the MAC are sampled by the PHY synchronously with respect to the MDC. Data signals written by the PHY are generated synchronously with respect to the MDC. This pin requires an external pull-up (1 k to 10 k). Management This pin is active-low and indicates an unmasked management interrupt. This pin requires an external pull-up Interface resistor (1 k to 4.7 k). Interrupt
MDINT_N
89
46
1. PHYAD description applies to the 128-TQFP only. For the 68-MLCC, the valid range will be 0--15.
Management Interrupt The ET1011 is capable of generating hardware interrupts on pin MDINT_N in response to a variety of user-selectable conditions. MDINT_N is an open-drain, active-low signal that can be wire-ORed with several other ET1011 devices. A single 2.2 k pull-up resistor is recommended for this wire-OR configuration. When an interrupt occurs, the system can poll the status of the interrupt status register on each device to determine the origin of the interrupt. There are nine conditions that can be selected to generate an interrupt:

Autonegotiation status change Autonegotiation page received FIFO overflow/underflow

Link status change High bit-error rate Full error counter

Local/remote rx status change Automatic speed downshift occurred MDIO synchronization lost
The ET1011 is configured to generate an interrupt based on any of these conditions by use of the interrupt mask register (MII register 24). By setting the corresponding bit in the interrupt mask register for the desired condition, the ET1011 will generate the desired interrupt. The ET1011 can be polled on the status of an activated interrupt condition by accessing MII register interrupt status register (MII register 25). If this condition has occurred, the corresponding bit in the interrupt status register will be set. The interrupt status register is self-clearing on a read operation. Agere Systems Inc. 27
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Hardware Interfaces (continued)
Configuration Interface
The hardware configuration pins initialize the ET1011 at poweron and reset. The configuration is latched during initialization and stored. These pins set the default value of their corresponding MII register bits. Some configuration inputs are shared with LED pins. The hardware configuration and LED pins are read on initial powerup of the ET1011, during a hardware reset and during recovery from hardware powerdown. The logic value at the pin is sensed and latched. After RESET_N has been deasserted (raised high), the shared configuration pins become outputs that are used to drive LEDs. Note: The 68-MLCC, unlike its 128-TQFP counterpart, offers comparatively limited hardware configuration capabilities. www..com It only has PAUSE, SYS_CLK_EN_N, and LPED_EN_N configuration pins. Most configuration settings are established via registers. Autonegotiation: Speed and Duplex Selection The ET1011 supports 10Base-T, 100Base-TX, and 1000Base-T modes in both full and half duplex. For the purpose of autonegotiation, the IEEE defines a technology as a combination of speed and duplex capability. The PHY can be configured to advertise a subset of the available technologies as shown in Table 10. Once autonegotiation is completed, an attempt is made to bring up a link with the highest common denominator technology. Table 10. Autonegotiation Modes SP_1000 0 0 0 0 1 1 0 0 1 1 1 1 1 1 SP_100 0 0 1 1 0 0 1 1 0 0 1 1 1 1 SP_10 1 1 0 0 0 0 1 1 1 1 0 0 1 1 DUPLEX 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Autonegotiation Mode Advertise only 10Base-T, half duplex. Advertise only 10Base-T, full duplex. Advertise only 100Base-TX, half duplex. Advertise only 100Base-TX, full duplex. Advertise only 1000Base-T, half duplex. Advertise only 1000Base-T, full duplex. Advertise 10Base-T and 100Base-TX, half duplex. Advertise 10Base-T and 100Base-TX, full duplex. Advertise 10Base-T and 1000Base-T, half duplex. Advertise 10Base-T and 1000Base-T, full duplex. Advertise 100Base-TX and 1000Base-T, half duplex. Advertise 100Base-TX and 1000Base-T, full duplex. Advertise all capabilities, half duplex. Advertise all capabilities, full duplex.
Autonegotiation can be disabled and the technology forced by writing to the control register (MI register address 0, bits 12). This causes the PHY to transmit and receive in accordance with the selected technology irrespective of the capability of the link partner. Disabling autonegotiation is not recommended.
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Hardware Interfaces (continued)
Autonegotiation: Master/Slave Configuration A PHY can advertise a preference for master or slave. The hardware configuration pin MAS_CFG sets the preference as shown in Table 11. If both PHYs advertise the same master/slave preference, the master/slave configuration is resolved during autonegotiation as described in the IEEE standards. Table 11. Master/Slave Preference MAS_CFG
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Autonegegotiation Master/Slave Mode Autonegotiation, advertise slave preference. Autonegotiation, advertise master preference.
0 1
The PHY can be manually configured for master or slave by writing to the 1000Base-T control register (MI register address 9, bits 12 and 11). If both PHYs are manually configured to the same master/slave setting, a 1000Base-T link cannot be established. Manual master/slave configuration is not recommended.
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Hardware Interfaces (continued)
Autonegotiation: MDI/MDI-X Configuration The PHY can be configured to automatically detect MDI/MDI-X configuration, or the MDI/MDI-X configuration can be forced as shown in Table 12. Table 12. MDI/MDI-X Configuration AUTO_MDI_EN 1 0 0 MDI_SEL X 0 1 MDI/MDI-X Configuration Automatic MDI/MDI-X detection. MDI configuration (NIC/DTE). MDI-X configuration (switch).
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Table 13. Configuration Signals Pin Name SPEED_1000 SPEED_100 SPEED_10 Pin # 128TQFP 82 83 84 Pin # Pin 68Description MLCC -- -- -- Functional Description
Speed 1000 The speed configuration pins set the default advertised speed. Speed 100 The assertion of each input enables advertisement of the correSpeed 10 sponding speed to the remote end. SPEED_1000 Advertise 1000Base-T SPEED_100 Advertise 100Base-TX SPEED_10 Advertise 10Base-T
DUPLEX
75
--
Duplex
The default is to advertise all three speeds. DUPLEX selects the duplex mode to be advertised (half or both half and full). 0 = Advertise half duplex. 1 = Advertise both half and full duplex (default). Enables the system clock. 0 = SYS_CLK enabled. 1 = SYS_CLK disabled (default). This input determines the master/slave preference. 0 = Advertise a preference to operate as slave (default). 1 = Advertise a preference to operate as master.
SYS_CLK_E N_N MAS_CFG
15
6
SYS_CLK Enable Master slave configuration
86
--
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TruePHY ET1011 Gigabit Ethernet Transceiver
Hardware Interfaces (continued)
Table 13. Configuration Signals (continued) Pin Name PAUSE Pin # 128TQFP 85 Pin # 68MLCC 43 Pin Description Pause Functional Description This input sets the pause mode. If PAUSE is asserted, full-duplex pause and asymmetric pause operation are advertised. 0 = Don't advertise pause (default). 1 = Advertise full-duplex pause and asymmetric pause. These inputs determine the MDI/MDI-X configuration. If AUTO_MDI_EN is asserted, automatic MDI/MDI-X detection is enabled and the MDI/MDI-X configuration is determined by the PHY automatically. The MDIX_SEL signal is ignored. If AUTO_MDI_EN is not asserted, MDIX_SEL determines the MDI/MDI-X configuration and MDIX_SEL high sets the MDIX configuration or MDIX_SEL low sets the MDI configuration. Autoconfigure MDI/MDI-X 0 = Automatic MDI/MDI-X detection disabled. 1 = Automatic MDI/MDI-X detection enabled (default). MDI/MDI-X Selection 0 = MDI configuration (default). 1 = MDI-X configuration mode.
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AUTO_MDI_ EN MDIX_SEL
21 74
-- --
Autoconfigure MDI/MDI-X MDI/MDI-X Selection
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Hardware Interfaces (continued)
Table 13. Configuration Signals (continued) Pin Name MAC_IF_ SEL[2:0] Pin # Pin # Pin 128-TQFP 68-MLCC Description 18 19 20 MAC Inter10 face Mode 9 (MAC_IF_ SEL[1:0] (See Note 1.) Functional Description This input selects the desired MAC interface mode. Configure the MAC during reset as follows: 000 = GMII/MII (128-TQFP default). 001 = TBI. 010 = GMII/MII (clocked by GTX_CLK instead of TX_CLK) 011 = Reserved. 100 = RGMII/RMII (trace delay; 68-MLCC default). 101 = RTBI (trace delay). 110 = RGMII/RMII (DLL delay). 111 = RTBI (DLL delay). LPED_EN_N enables the low-power energy-detect (LPED) mode when COMA is asserted. When the PHY is in LPED mode, it can wake the MAC/controller (instead of Magic Packet) by asserting the MDINT_N pin to indicate the presence of cable energy. 0 = Low-power energy-detect mode enable. 1 = Low-power energy-detect mode disabled (default). Connect a 1.0 k precision resistor to ground to set termination for all digital I/O's.
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LPED_EN_N
16
7
Low Power Energy Detection Enable
PRES
87
44
Precision Resistor
1. In the 68-MLCC, MAC_IF_SEL 2 (=1) will be set internally.
LEDs Interface
The ET1011 is capable of sinking or sourcing current to drive LEDs. These LEDs are used to provide link status information to the user. The ET1011 is capable of automatically sensing the polarity of the LEDs. The device determines the active sense of the LED based upon the input that is latched during configuration. Thus, if logic 1 is read, the device will drive the pin to ground to activate the LED; otherwise, it will drive the pin to supply to activate the LED. The LEDs can be programmed to stretch out events to either 28, 60, or 100 ms. This makes very short events more visible to the user. All LEDs can be programmed to be on, off, or blink instead of the default status function. This is useful for alternative function indication under host processor control: for example, a system error during power-on self-check. Four of the LEDs (LED_ACT, LED_LNK1, LED_100 and LED_10001) can be programmed to indicate one of thirteen different status functions instead of the default status function:

1000Base-T 100Base-TX 10Base-T 1000Base-T (on) and 100Base-TX (blink) Link established Transmit activity Receive activity

Transmit or receive activity Full duplex Collision Link established (on) and activity (blink) Link established (on) and receive activity (blink) Full duplex (on) and collision (blink)
The LED drivers can be configured by use of LED control register 1 and LED control register 2 (MII registers 27--28).
1. Only LED_LNK and LED_1000 are available in the 68-pin MLCC.
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Hardware Interfaces (continued)
Table 14. LED Pin Name LED_1000 LED_100 LED_10
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Pin # 128-TQFP 82 83 84 75 85 86
Pin # 68-MLCC 42 -- -- -- 43 --
Pin Description 1000Base-T LED 100Base-TX LED 10Base-T LED Duplex LED Link Established LED Collision LED
Functional Description This LED indicates that the device is operating in 1000Base-T mode. Setting can be overridden. This LED indicates that the device is operating in 100Base-TX mode. Setting can be overridden. This LED indicates that the device is operating in 10Base-T mode. Setting can be overridden. This LED indicates that the device is operating in fullduplex mode. Setting can be overridden. This LED indicates that the link is established. Setting can be overridden. This LED indicates that both transmit and receive activity is occurring in half-duplex mode. Setting can be overridden. This LED indicates that there is transmit or receive activity. Setting can be overridden.
LED_LNK LED_COL
LED_ACT
74
--
Transmit/Receive Activity LED
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Hardware Interfaces (continued)
Media-Dependent Interface: Transformer Interface
Table 15. Transformer Interface Signals Pin Name TRD[0]+ TRD[0]- Pin # 128-TQFP 39 41 Pin # 68-MLCC 19 20 Pin Description Transmit and Receive Differential Pair 0 Functional Description Connect this signal pair through a transformer to the media-dependent interface. In 1000Base-T mode, transmit and receive occur simultaneously at TRD[0]. In 10Base-T and 100Base-TX modes, TRD[0] are used to transmit when operating in the MDI configuration and to receive when operating in the MDI-X configuration. The PHY automatically determines the appropriate MDI/MDI-X configuration. Connect this signal pair through a transformer to the media dependent interface. In 1000Base-T mode, transmit and receive occurs simultaneously at TRD[1]. In 10Base-T and 100Base-TX modes, TRD[1] are used to receive when operating in the MDI configuration and to transmit when operating in the MDI-X configuration. The PHY automatically determines the appropriate MDI/MDI-X configuration. Connect this signal pair through a transformer to the media-dependent interface. In 1000Base-T mode, transmit and receive occurs simultaneously at TRD[2]. In 10Base-T and 100Base-TX modes, TRD[2] are unused. Connect this signal pair through a transformer to the media-dependent interface. In 1000Base-T mode, transmit and receive occurs simultaneously at TRD[3]. In 10Base-T and 100Base-TX modes, TRD[3] are unused. RSET sets an absolute value reference current for the transmitter. Connect this signal to analog ground through a precision 6.34 k 1% resistor.
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TRD[1]+ TRD[1]-
45 47
21 22
Transmit/Receive Differential Pair 1
TRD[2]+ TRD[2]-
54 56
28 29
Transmit/Receive Differential Pair 2
TRD[3]+ TRD[3]-
60 62
31 32
Transit/Receive Differential Pair 3
RSET
52
26
Analog Reference Resistor
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TruePHY ET1011 Gigabit Ethernet Transceiver
Hardware Interfaces (continued)
Clocking and Reset
Table 16. Clocking and Reset Pin Name CLK_IN XTAL_1
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Pin # 128-TQFP 31 31 32
Pin # 68-MLCC 16 16 17
Pin Description Reference Clock Input Reference Crystal Input Reference Crystal Input System Clock
Functional Description Connect this signal to a 25 MHz clock input (CLK_IN) or a 25 MHz 50 ppm tolerance crystal (XTAL_1).
SYS_CLK
94
50
Connect this signal to a 25 MHz 50 ppm tolerance crystal. Float this signal if an external clock is used (CLK_IN). Use this signal to supply a 125 MHz clock to the MAC. By default, the SYS_CLK output is disabled. The SYS_CLK output can be enabled by asserting the SYS_CLK_EN_N pin or via the management interface. Drive RESET_N low for 1 s to initiate a hardware reset. The ET1011 completes all reset operations within 5 ms of this signal returning to a high state. The configuration pins and the physical address configuration are read during a hardware reset. Drive COMA high to initiate a hardware powerdown. The ET1011 completes all reset operations within 5 ms of this signal returning to a low state. All hardware functions are disabled during a hardware powerdown. The configuration pins and the physical address configuration are read during a hardware powerdown.
RESET_N
34
18
Reset
COMA
25
12
Hardware Powerdown
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Hardware Interfaces (continued)
JTAG
The ET1011 has a standard IEEE 1149.1 JTAG test interface. The interface provides extensive test and diagnostics capability. It contains internal circuitry that allows the device to be controlled through the JTAG port to provide on-chip, in-circuit emulation. The JTAG interface is a bidirectional serial interface with its own reset strobe (TRST_N). The reset strobe can be used independently to reset the JTAG state machine but must be used during a power-on reset (see Reset Timing on page 73). The only exception is when the JTAG interface is not being used. In this scenario, connect the reset strobe to ground to keep the interface in the reset state.
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Test Interface Pin # 128-TQFP 16 Pin # 68-MLCC 7 Pin Description Test Data Input Functional Description This signal is the JTAG serial input. All instructions and scanned data are input using this pin. This pin has an internal pull-up resistor. This signal is the JTAG serial output. Scanned data and status bits are output using this pin.This pin has an internal pull-up resistor. This signal is the JTAG serial shift clock. It clocks all of the data that passes through the port on TDI and TDO. This signal is the JTAG test mode control. This pin has an internal pull-up resistor. A high-to-low transition on this signal causes the JTAG TAP controller to enter the reset state. This pin has an internal pull-down resistor.
Pin Name TDI
TDO
17
8
Test Data Output
TCK
10
2
Test Clock
TMS TRST_N
15 14
6 5
Test Mode Select Test Reset (Jtag Reset)
Regulator Control
The ET1011 has two on-chip regulator controllers. This allows the device to be powered from a single supply, either 3.3 V or 2.5 V. The on-chip regulator control circuits provide output control voltages that are used to control two external transistors and thus provide regulated 1.0 V and 2.5 V supplies. Table 18. Regulator Control Interface Pin Name CTRL_1V0 Pin # 128-TQFP 79 Pin # 68-MLCC 40 Pin Description Regulator Control for 1.0 V Regulator Control for 2.5 V Functional Description This is the regulator output control voltage for the 1.0 V supply. It is used to control an external transistor and thus provide a regulated 1.0 V supply. This is the regulator output control voltage for the 2.5 V supply. It is used to control an external transistor and thus provide a regulated 2.5 V supply.
CTRL_2V5
78
39
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TruePHY ET1011 Gigabit Ethernet Transceiver
Hardware Interfaces (continued)
Regulator Control (continued)
The ET1011 digital and analog core operates at 1.0 V. The analog I/O operates at 2.5 V. The digital I/O can operate at either 3.3 V or 2.5 V. The GMII interface operates at 3.3 V and the RGMII interface operates at 2.5 V. The onchip regulator control allows the device to be operated from a wide variety of external supply combinations. When more than one external supply is available, one or both of the regulator control circuits may be left unused. Table 19 lists example combinations of available external supplies and shows how the on-chip regulator control may be used to provide the required supplies. Table 19. Supply Voltage Combinations
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Available External Supplies 3.3 V only
AVDDL 1.0
DVDD 1.0
AVDDH 2.5
DVDDIO
Description
3.3 or 2.5 Digital I/O can be either 3.3 V or 2.5 V. Regulator control is used to provide 1.0 V and 2.5 V. 2.5 Digital I/O is 2.5 V. Regulator control is used to provide 1.0 V.
2.5 V only 3.3 V and 1.0 V 2.5 V and 1.0 V 3.3 V and 2.5 V 3.3 V, 2.5 V, and 1.0 V
1.0 1.0 1.0 1.0 1.0
1.0 1.0 1.0 1.0 1.0
2.5 2.5 2.5 2.5 2.5
3.3 or 2.5 Digital I/O can be either 3.3 V or 2.5 V. Regulator control is used to provide 2.5 V. 2.5 Digital I/O is 2.5 V. Regulator control is not required.
3.3 or 2.5 Digital I/O can be either 3.3 V or 2.5 V. Regulator control is used to provide 1.0 V. 3.3 or 2.5 Digital I/O can be either 3.3 V or 2.5 V. Regulator control is not required.
Power, Ground, and No Connect
Table 20. Power, Ground, and No Connect Pin Name DVDDIO DVDD DVSS AVDDH AVDDL AVSS NC Pin Description VDD VDD VSS VDD VDD VSS No Connect Functional Description Digital I/O 3.3 V or 2.5 V supply. Digital core 1.0 V supply. Digital ground1. Analog power 2.5 V. Analog power 1.0 V. Analog ground1. Reserved--do not connect.
1. For the 68-MLCC, all AVSS and DVSS pins share a common ground pin (exposed pad) in the center of the device.
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Cable Diagnostics
The ET1011 has on-chip cable diagnostics. The cable analysis uses two distinct methods for evaluating the cable: link analysis and time domain reflectometry (TDR) analysis. This analysis can be used to detect cable impairments that may be preventing a gigabit link or affecting performance. When there is a link active, the link analysis can detect cable length, link quality, pair skew, pair swaps (MDI/MDI-X configuration), and polarity reversal. When there is no link, TDR can detect cable faults (open circuit, short circuit), distance to the fault, pair fault is on, cable length, pair skew, and excessive crosstalk. Table 21 summarizes the specifications of the cable diagnostic functions. Table 21. Cable Diagnostic Functions Feature www..com Description 10 -- -- -- 100 -- -- -- 1000 -- -- --
1
Term
Unterm
Analysis Line Probing
Detection of Cable Fault on Cable open Any Pair Cable short Indicate distance to fault Pair swaps Detect Polarity Reversal Good Cable with Link Good Cable Without Link Pair Skew with Link Pair Skew Without Link Excessive Crosstalk -- Indicate length Indicate length Detect excessive, >50 ns Detect excessive, >50 ns Cable quality or split pairs
2 m -- -- -- 5 m --
3
2 m -- -- -- 2 m -- Link Analysis Link Analysis Link Analysis Line Probing Link Analysis Line Probing Line Probing
-- -- -- -- -- --
2
5 m -- -- -- --
5 m --
-- --
3
1. Pair swaps on C and D as well as pairs A and B are reported. 2. Polarity reversal in 100Base-TX is not detected because MLT-3 signaling is polarity insensitive. 3. If the magnitude of the peak reflection is greater than 15% of an open circuit.
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TruePHY ET1011 Gigabit Ethernet Transceiver
Register Description
Register Address Map
Table 22. Register Address Map Address 0 1 2 3 4 5 6 7 8 9 10 11--14 15 16--18 19 20 21 22 23 24 25 26 27 28 29-31 Description Control register. Status register. PHY identifier register 1. PHY identifier register 2. Autonegotiation advertisement register. Autonegotiation link partner ability register. Autonegotiation expansion register. Autonegotiation next page transmit register. Link partner next page register. 1000Base-T control register. 1000Base-T status register. Reserved. Extended status register. Reserved. Loopback control register. Reserved. Register management (MI) control register. PHY configuration register. PHY control register. Interrupt mask register. Interrupt status register. PHY status register. LED control register 1. LED control register 2. Reserved.
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Table 23. Register Type Definition Type LL LH R/W RO SC Description Latching low. Latching high. Read write. Register can be read or written. Read only. Register is read only. Writes to register are ignored. Self-clearing. Register is self-clearing; if a one is written, the register will automatically clear to zero after the function is completed.
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Register Description (continued)
Register Functions/Settings Table 24. Control Register--Address 0 Control Register Bit 15 Reset Name Description Type R/W SC R/W Default 0 0 Notes 1 2 3 1 = PHY reset. 0 = Normal operation. 14 Loopback 1 = Enable loopback. 0 = Disable loopback. www..com 13 Speed Selection Bit 6,13. (LSB) 11 = Reserved. 10 = 1000 Mbits/s. 01 = 100 Mbits/s. 00 = 10 Mbits/s. 12 Autonegotiation 1 = Enable autonegotiation process. Enable 0 = Disable autonegotiation process. 11 Powerdown 1 = Powerdown. 0 = Normal operation. 10 Isolate 1 = Isolate PHY from MII. 0 = Normal operation. 9 Restart Autonegoti- 1 = Restart autonegotiation process. ation 0 = Normal operation. 8 Duplex Mode 1 = Full duplex. 0 = Half duplex. 7 Collision Test 1 = Enable collision test. 0 = Disable collision test. 6 Speed Selection See bit 13. (MSB) 5:0 Reserved --
R/W SPEED_1000 SPEED_100 SPEED_10
R/W R/W R/W R/W SC R/W R/W R/W RO
1 0 0 0 DUPLEX 0 See bit 13 0
4 -- 5 -- 6 7 3 --
1. The reset bit is automatically cleared upon completion of the reset sequence. This bit is set to 1 during reset. 2. This is the master enable for digital and analog loopback as defined by the standard. The exact type of loopback is determined by the loopback control register (address 19). 3. The speed selection address 0 bits 13 and 6 may be used to configure the link manually. Setting these bits has no effect unless address 0 bit 12 is clear. The speed bits are set by the SPEED_10, SPEED_100, and SPEED_1000 pins at reset. 4. When this bit is cleared, the link configuration is determined manually. 5. Setting this bit isolates the PHY from the MII, GMII, or RGMII interfaces. 6. This bit may be used to configure the link manually. Setting this bit has no effect unless address 0 bit 12 is clear. Duplex is set on reset by the DUPLEX pin. 7. Enables IEEE 22.2.4.1.9 collision test.
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TruePHY ET1011 Gigabit Ethernet Transceiver
Register Description (continued)
Table 25. Status Register--Address 1 Status Register Bit 15 14 13
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Name 100Base-T4 100Base-X Full Duplex 100Base-X Half Duplex 10Base-T Full-Duplex 10Base-T Half-Duplex 100Base-T2 Full-Duplex 100Base-T2 Half-Duplex Extended Status Reserved
Description 0 = Not 100Base-T4 capable. 1 = 100Base-X full-duplex capable. 0 = Not 100Base-X full-duplex capable. 1 = 100Base-X half-duplex capable. 0 = Not 100Base-X half-duplex capable. 1 = 10Base-T full-duplex capable. 0 = Not 10Base-T full-duplex capable. 1 = 10Base-T half-duplex capable. 0 = Not 10Base-T half-duplex capable. 0 = Not 100Base-T2 full-duplex capable. 0 = Not 100Base-T2 half-duplex capable. 1 = Extended status information in register 0Fh. --
Type RO RO RO RO RO RO RO RO RO RO RO RO LH RO RO LL RO LH RO
Default 0 SPEED_100 and DUPLEX SPEED_100 SPEED_10 and DUPLEX SPEED_10 0 0 1 -- 1 0 0 1 0 0 1
Notes 1 2 2 2 2 -- -- -- -- -- 3 4 -- 5 -- 6
12 11 10 9 8 7 6 5 4 3 2 1 0
MF Preamble Suppression 1 = Preamble suppressed management frames accepted. Autonegotiation Complete Remote Fault Autonegotiation Ability Link Status Jabber Detect Extended Capability 1 = Autonegotiation process complete. 0 = Autonegotiation process not complete. 1 = Remote fault detected. 0 = No remote fault detected. 1 = Autonegotiation capable. 0 = Not autonegotiation capable. 1 = Link is up. 0 = Link is down. 1 = Jabber condition detected. 0 = No jabber condition detected. 1 = Extended register capabilities.
1. The ET1011 does not support 100Base-T4 or 100Base-T2, therefore, these register bits will always be set to zero. 2. These bits receive values from the SPEED_10, SPEED_100, SPEED_1000, and DUPLEX pins during reset as follows: Register Bit 14 13 12 11 SPEED_100 SPEED_10 and DUPLEX SPEED_10 Configuration Pin Combination SPEED_100 and DUPLEX
3. Upon completion of autonegotiation, this bit becomes set. 4. This bit indicates that a remote fault has been detected. Once set, it remains set until it is cleared by reading register 1 via the management interface or by PHY reset. 5. This bit indicates that a valid link has been established. Once cleared due to link failure, this bit will remain cleared until register 1 is read via the management interface. 6. Indicates that the PHY provides an extended set of capabilities that may be accessed through the extended register set. For a PHY that incorporates a GMII/RGMII, the extended register set consists of all management registers except registers 0, 1, and 15.
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Register Description (continued)
Table 26. PHY Identifier Register 1--Address 2 PHY Identifier Register 1 Bit 15:0 Name PHY Identifier Bits 3:18 Description Organizationally unique identifier (OUI), bits 3:18. Type RO Default 0x0282 Notes 1
Table 27. PHY Identifier Register 2--Address 3 PHY Identifier Register 2
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Bit
Name
Description Organizationally unique identifier (OUI), bits 19:24. Model number = 1. Revision number = 2.
Type RO RO RO
Default 111100 000001 0010
Notes 1 -- --
15:10 9:4 3:0
PHY Identifier Bits 19:24 Model Number Revision Number
1. Agere's OUI is 00-05-3D.
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TruePHY ET1011 Gigabit Ethernet Transceiver
Register Description (continued)
Table 28. Autonegotiation Advertisement Register--Address 4 Autonegotiation Advertisement Register 1 Bit 15 14 13
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Name Next Page Reserved Remote Fault Reserved
Description 1 = Advertise next page ability supported. 0 = Advertise next page ability not supported. -- 1 = Advertise remote fault detected. 0 = Advertise no remote fault detected. --
Type R/W RO R/W RO R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 PAUSE PAUSE 0 SPEED_100 and DUPLEX SPEED_100 SPEED_10 and DUPLEX SPEED_10 00001
Notes -- -- -- -- 1 1 2 3 3 3 3 --
12 11 10 9 8 7 6 5 4:0
Asymmetric Pause 1 = Advertise asymmetric pause ability. 0 = Advertise no asymmetric pause ability. Pause Capable 1 = Capable of full-duplex pause operation. 0 = Not capable of pause operation.
100Base-T4 Capa- 1 = 100Base-T4 capable. bility 0 = Not 100Base-T4 capable. 100Base-TX FullDuplex Capable 100Base-TX HalfDuplex Capable 10Base-T FullDuplex Capable 10Base-T HalfDuplex Capable Selector Field 1 = 100Base-TX full-duplex capable. 0 = Not 100Base-TX full-duplex capable. 1 = 100Base-TX half-duplex capable. 0 = Not 100Base-TX half-duplex capable. 1 = 10Base-T full-duplex capable. 0 = Not 10Base-T full-duplex capable. 1 = 10Base-T half-duplex capable. 0 = Not 10Base-T half-duplex capable. 00001 = IEEE 802.3 CSMA/CD.
1. Value read from PAUSE on reset. 2. The ET1011 does not support 100Base-T4, so the default value of this register bit is zero. 3. These bits receive values from the configuration pins upon reset as follows: Register Bit 8 7 6 5 SPEED_100 SPEED_10 and DUPLEX SPEED_10 Configuration Pin Combination SPEED_100 and DUPLEX
Note: Any write to this register prior to the completion of autonegotiation is followed by a restart of autonegotiation. Also note that this register is not updated following autonegotiation.
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Preliminary Data Sheet April 2004
Register Description (continued)
Table 29. Autonegotiation Link Partner Ability Register--Address 5 Autonegotiation Link Partner Ability Register Bit 15 Name Next page Description Type RO RO RO RO RO Default 0 0 0 0 0 Notes -- -- -- -- -- 1 = Link partner has next page ability. 0 = Link partner does not have next page ability. 14 Acknowledge 1 = Link partner has received link code word. 0 = Link partner has not received link code word. 13 Remote Fault 1 = Link partner has detected remote fault. 0 = Link partner has not detected remote fault. www..com 12 Reserved -- 11 Asymmetric 1 = Link partner desired asymmetric pause. Pause 0 = Link partner does not desire asymmetric pause. 10 Pause Capable 1 = Link partner capable of full-duplex pause operation. 0 = Link partner is not capable of pause operation. 9 100Base-T4 1 = Link partner is 100Base-T4 capable. Capability 0 = Link partner is not 100Base-T4 capable. 8 100Base-TX Full- 1 = Link partner is 100Base-TX full-duplex capaDuplex Capable ble. 0 = Link partner is not 100Base-TX full-duplex capable. 7 100Base-TX Half- 1 = Link partner is 100Base-TX half-duplex capaDuplex Capable ble. 0 = Link partner is not 100Base-TX half-duplex capable. 6 10Base-T Full1 = Link partner is 10Base-T full-duplex capable. Duplex Capable 0 = Link partner is not 10Base-T full-duplex capable. 5 10Base-T Half1 = Link partner is 10Base-T half-duplex capable. Duplex Capable 0 = Link partner is not 10Base-T half-duplex capable. 4:0 Protocol Selector Link partner protocol selector field. Field
RO
0
--
RO RO
0 0
-- --
RO
0
--
RO
0
--
RO
0
--
RO
0
--
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Preliminary Data Sheet April 2004
TruePHY ET1011 Gigabit Ethernet Transceiver
Register Description (continued)
Table 30. Autonegotiation Expansion Register--Address 6 Autonegotiation Expansion Register Bit 15:5 4 3
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Name Reserved Parallel Detection Fault Link Partner Next Page Ability
Description
Type RO RO LH RO
Default -- 0 0
Notes -- -- --
2
1
0
-- 1 = Parallel link fault detected. 0 = Parallel link fault not detected. 1 = Link partner has next page capability. 0 = Link partner does not have next page capability. Next Page Capa- 1 = Local device has next page capability. bility 0 = Local device does not have next page capability. Page Received 1 = New page has been received from link partner. 0 = New page has not been received. Link Partner Auto- 1 = Link partner has autonegotiation capability. negotiation Ability 0 = Link partner does not have autonegotiation capability.
RO LH RO LH RO
1
--
0
--
0
--
Table 31. Autonegotiation Next Page Transmit Register--Address 7 Autonegotiation Next Page Transmit Register Bit 15 14 13 12 11 Name Next Page Reserved Message Page Acknowledge 2 Toggle Description 1 = Additional next pages follow. 0 = Sending last next page. -- 1 = Formatted page. 0 = Unformatted page. 1 = Complies with message. 0 = Cannot comply with message. 1 = Previous value of transmitted link code word was logic zero. 0 = Previous value of transmitted link code word was logic one. Next page message code or unformatted data. Type R/W RO R/W R/W RO Default 0 0 1 0 0 Notes -- -- -- -- --
10:0
Message/ Unformatted Code Field
R/W
1
--
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TruePHY ET1011 Gigabit Ethernet Transceiver
Preliminary Data Sheet April 2004
Register Description (continued)
Table 32. Link Partner Next Page Register--Address 8 Link Partner Next Page Register Bit 15 14 13 12 11 Name Next Page Acknowledge Message Page Acknowledge 2 Description 1 = Additional next pages follow. 0 = Sending last next page. 1 = Acknowledge. 0 = No acknowledge. 1 = Formatted page. 0 = Unformatted page. 1 = Complies with message. 0 = Cannot comply with message. 1 = Previous value of transmitted link code word was logic zero. 0 = Previous value of transmitted link code word was logic one. Next page message code or unformatted data. Type RO RO R/W R/W RO Default 0 0 0 0 0 Notes -- -- -- -- --
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Toggle
10:0
Message/ Unformatted Code Field
R/W
0
--
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Preliminary Data Sheet April 2004
TruePHY ET1011 Gigabit Ethernet Transceiver
Register Description (continued)
Table 33. 1000 Base-T Control Register--Address 9 1000Base-T Control Register Bit 15:13 Name Test Mode Description 000 = Normal mode. 001 = Test mode 1--transmit waveform test. 010 = Test mode 2--master transmit jitter test. 011 = Test mode 3--slave transmit jitter test (slave mode). 100 = Test mode 4--transmit distortion test. 101, 110, 111 = Reserved. 1 = Enable master/slave configuration. 0 = Automatic master/slave configuration. 1 = Configure PHY as master. 0 = Configure PHY as slave. 1 = Prefer multiport device (master). 0 = Prefer single-port device (slave). 1 = Advertise 1000Base-T full-duplex capability. 0 = Advertise no 1000Base-T full-duplex capability. Type R/W Default 000 Notes --
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12
11
10 9
Master/Slave Configuration Enable Master/Slave Configuration Value Port Type Advertise 1000Base-T Full-duplex Capability Advertise 1000Base-T Half-duplex Capability Reserved
R/W
0
--
R/W
MAS_CFG
1
R/W R/W
MAS_CFG SPEED_1000 and DUPLEX
2 3
8
1 = Advertise 1000Base-T half-duplex capability. 0 = Advertise no 1000Base-T half-duplex capability.
R/W
SPEED_1000
4
7:0
--
RO
9.7:0
--
1. Value read from MAS_CFG pin at reset. Setting this bit has no effect unless address 9 bit 12 is set. 2. Value read from MAS_CFG at reset. 3. Value is a result of (SPEED_1000 and DUPLEX) pins at reset. 4. Value read from SPEED_1000 pin at reset. Note: Logically, bits 12:8 may be regarded as an extension of the technology ability field of register 4.
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TruePHY ET1011 Gigabit Ethernet Transceiver
Preliminary Data Sheet April 2004
Register Description (continued)
Table 34. 1000Base-T Status Register--Address 10 1000Base-T Status Register Bit 15 Name Description 1 = Master/slave configuration fault detected. 0 = No master/slave configuration fault detected. 1 = Local PHY resolved to master. 0 = Local PHY resolved to slave. 1 = Local receiver okay. 0 = Local receiver not okay. 1 = Remote receiver okay. 0 = Remote receiver not okay. 1 = Link partner is capable of 1000Base-T full duplex. 0 = Link partner not 1000Base-T full-duplex capable. Type RO, LH, SC RO Default 0 Notes 1 Master/ Slave Configuration Fault 14 Master/Slave Configuration Resolution www..com 13 Local Receiver Status 12 Remote Receiver Status 11 Link Partner 1000Base-T Full-duplex Capability 10 Link Partner 1000Base-T Half-duplex Capability 9:8 Reserved 7:0 Idle Error Count
0
2
RO RO RO
0 0 0
-- -- 3
1 = Link partner is 1000Base-T half-duplex capable. 0 = Link partner not 1000Base-T half-duplex capable.
RO
0
3
-- MSB of idle error count.
RO RO
0
-- 4
1. Once set, this bit remains set until cleared by the following actions: Read of register 10 via the management interface. Reset. Completion of autonegotiation. Enable of autonegotiation. 2. This bit is not valid when bit 15 is set. 3. Note that logically, bits 11:10 may be regarded as an extension of the technology ability field of register 5. 4. These bits contain a cumulative count of the errors detected when the receiver is receiving idles and both local and remote receiver status are OK. The count is held at 255 in the event of overflow and is reset to zero by reading register 10 via the management interface or by reset.
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TruePHY ET1011 Gigabit Ethernet Transceiver
Register Description (continued)
Table 35. Reserved Registers--Addresses 11--14 Reserved Registers Bit 15:0 Name Reserved Description -- Type -- Default -- Notes --
Table 36. Extended Status Register--Address 15 Extended Status Register
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Bit 15 14 13 12
Name 1000Base-X Fullduplex 1000Base-X Halfduplex 1000Base-T Fullduplex 1000Base-T Halfduplex Reserved
Description 0 = Not 1000Base-X full-duplex capable. 0 = Not 1000Base-X half-duplex capable. 1 = 1000Base-T full-duplex capable. 0 = Not 1000Base-T full-duplex capable. 1 = 1000Base-T half-duplex capable. 0 = Not 1000Base-T half-duplex capable. --
Type RO RO RO RO RO
Default 0 0 SPEED_1000 and DUPLEX SPEED_1000 0
Notes 1 -- 2 3 --
11:0
1. 1000Base-X not supported. 2. Value is a result of (SPEED_1000 and DUPLEX) pins at reset. 3. Value read from SPEED_1000 pin at reset.
Table 37. Reserved Registers--Addresses 16--18 Reserved Registers Bit 15:0 Name Reserved Description -- Type -- Default -- Notes --
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TruePHY ET1011 Gigabit Ethernet Transceiver
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Register Description (continued)
Table 38. Loopback Control Register--Address 19 Loopback Control Register Bit 15 14 13 12 11 10 9:0 Name MII Enable PCS Enable PMD Enable All Digital Enable Description 1 = Use MII loopback. 0 = MII loopback disabled. 1 = Use PCS loopback. 0 = PCS loopback disabled. 1 = Use PMD loopback. 0 = PMD loopback disabled. 1 = Use all digital loopback. 0 = All digital loopback disabled. 1 = Use replica loopback. 0 = Replica loopback disabled. 1 = Use line driver loopback. 0 = Line driver loopback disabled. -- Type R/W R/W R/W R/W R/W R/W -- Default 1 0 0 0 0 0 -- Notes -- -- 1 -- -- -- --
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Replica Enable Line Driver Enable Reserved
1. Only for 100Base-TX.
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Preliminary Data Sheet April 2004
TruePHY ET1011 Gigabit Ethernet Transceiver
Register Description (continued)
Table 39. Reserved Registers--Address 20 Reserved Registers Bit 15:0 Name Reserved Description -- Type -- Default -- Notes --
Table 40. Management Interface (MI) Control Register--Address 21 Management Interface (MI) Control Register
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Bit
Name Reserved MI Error Counter Reserved Ignore 10G Frames
Description -- MI transaction error count (00-7F). -- 1 = Management frames with ST = <00> are ignored. 0 = Management frames with ST = <00> are treated as wrong frames -- 1 = MI preamble is ignored. 0 = MI preamble is required.
Type -- RO -- R/W
Default -- 00 -- 1
Notes -- -- -- --
15:11 10:4 3 2
1 0
Reserved Preamble Suppression Enable
-- R/W
-- 1
-- --
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TruePHY ET1011 Gigabit Ethernet Transceiver
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Register Description (continued)
Table 41. PHY Configuration Register--Address 22 PHY Configuration Register Bit 15 Name CRS Transmit Enable Description Type R/W Default 0 Notes -- 1 = Enable CRS on transmit in half-duplex mode. 0 = Disable CRS on transmit. 14 Reserved -- 13:12 Transmit FIFO depth 00 = 8. (1000Base-T) 01 = 16. www..com 10 = 24. 11 = 32. 11:10 Automatic Speed 00 = Disable automatic speed downshift. Downshift Mode 01 = 10Base-T downshift enabled. 10 = 100Base-TX downshift enabled. 11 = 100Base-TX and 10Base-T enabled. 9 TBI Detect Select 1 = CRS pin outputs comma detect. 0 = CRS pin outputs link status detect 8 TBI Rate Select 1 = Output 125 MHz clock on RX_CLK while COL is held low (full rate). 0 = Output even/odd clocks on RX_CLK/COL 7 Alternate Next-Page 1 = Enables manual control of 1000Base-T next pages only. 0 = Normal operation of 1000Base-T next page exchange 6 Group MDIO Mode 1 = Enable group MDIO mode. Enable 0 = Disable Group MDIO mode. 5 Transmit Clock 1 = Enable output of 1000Base-T transmit Enable clock (TX_CLK pin). 0 = Disable output. 4 System Clock Enable 1 = Enable output of 125 MHz reference clock (SYS_CLK pin). 0 = Disable output of 125 MHz reference clock. 3 Reserved -- 2:0 MAC Interface Mode 000 = GMII/MII Select 001 = TBI 010 = GMII/MII clocked by GTX_CLK instead of TX_CLK 011 = Reserved. 100 = RGMII/RMII (trace delay). 101 = RTBI (trace delay). 110 = RGMII/RMII (DLL delay). 111 = RTBI (DLL delay).
-- R/W
-- 01
-- --
R/W
11
1
R/W R/W
0 0
-- --
R/W
0
--
R/W R/W
0 0
-- --
R/W
SYS_CLK_EN_N
2
-- R/W
-- MAC_IF_SEL [2:0]
-- 3
1. If automatic speed downshift is enabled and the PHY fails to autonegotiate at 1000Base-T, the PHY will fall back to attempt connection at 100Base-TX and, subsequently, 10Base-T. This cycle will repeat. If the link is broken at any speed, the PHY will restart this process by reattempting connection at the highest possible speed (e.g., 1000Base-T). 2. Value is read from inversion of SYS_CLK_EN_N at reset. 3. For the 68-pin MLCC, only RGMII/RMII and RTBI modes/options are supported.
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TruePHY ET1011 Gigabit Ethernet Transceiver
Register Description (continued)
Table 42. PHY Control Register--Address 23 PHY Control Register Bit 15 14 13 12:11
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Name Reserved TDR_EN Reserved Automatic Speed Downshift Attempts Before Downshift Reserved Jabber (10Base-T) SQE (10Base-T) TP_LOOPBACK (10Base-T) Preamble Generation Enable Reserved Force Interrupt
Description -- 1 = Enable cable diagnostics. 0 = Disable cable diagnostics. -- 00 = 1. 01 = 2. 10 = 3. 11 = 4. -- 1 = Disable jabber. 0 = Normal operation. 1 = Enable heartbeat. 0 = Disable heartbeat. 1 = Disable TP loopback during half-duplex. 0 = Normal operation. 1 = Enable preamble generation for 10Base-T. 0 = Disable preamble generation for 10Base-T. -- 1 = Assert MDINT_N pin. 0 = Deassert MDINT_N pin.
Type -- R/W -- R/W
Default -- 0 -- 01
Notes -- 1 -- --
10:6 5 4 3 2 1 0
-- R/W R/W R/W R/W -- R/W
-- 0 0 1 1 -- 0
-- -- -- -- -- -- --
1. If TDR is enabled, the PHY can implement cable diagnostics and IP phone detection.
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TruePHY ET1011 Gigabit Ethernet Transceiver
Preliminary Data Sheet April 2004
Register Description (continued)
Table 43. Interrupt Mask Register--Address 24 Interrupt Mask Register Bit 15:10 9 Name Reserved MDIO Sync Lost Description -- Type -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default -- 0 0 0 0 0 0 0 0 0 0 Notes -- -- -- -- -- -- -- -- -- -- --
1 = Interrupt enabled. 0 = Interrupt disabled. 8 Autonegotiation 1 = Interrupt enabled. Status Change 0 = Interrupt disabled. 7 High Bit-Error 1 = Interrupt enabled. www..com Rate 0 = Interrupt disabled. 6 Next Page 1 = Interrupt enabled. Received 0 = Interrupt disabled. 5 Error Counter Full 1 = Interrupt enabled. 0 = Interrupt disabled. 4 FIFO Overflow/ 1 = Interrupt enabled. Underflow 0 = Interrupt disabled. 3 Receive Status 1 = Interrupt enabled. Change 0 = Interrupt disabled. 2 Link Status 1 = Interrupt enabled. Change 0 = Interrupt disabled. 1 Automatic Speed 1 = Interrupt enabled. Downshift 0 = Interrupt disabled. 0 Interrupt Enable 1 = Interrupt enabled. 0 = Interrupt disabled.
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Preliminary Data Sheet April 2004
TruePHY ET1011 Gigabit Ethernet Transceiver
Register Description (continued)
Table 44. Interrupt Status Register--Address 25 Interrupt Status Register Bit 15:10 9 Name Reserved MDIO Sync Lost Description -- Type Default Notes -- RO SC RO SC RO SC RO SC RO SC RO SC RO SC RO SC RO SC RO SC -- 0 0 0 0 0 0 0 0 0 0 -- 1 -- -- -- -- -- -- -- -- 2
1 = Event has occurred. 0 = Event has not occurred. 8 Autonegotiation 1 = Event has occurred. Status Change 0 = Event has not occurred. 7 High Bit-Error 1 = Event has occurred. www..com Rate 0 = Event has not occurred. 6 Next Page 1 = Event has occurred. Received 0 = Event has not occurred. 5 Error Counter Full 1 = Event has occurred. 0 = Event has not occurred. 4 FIFO Overflow/ 1 = Event has occurred. Underflow 0 = Event has not occurred. 3 Receive Status 1 = Event has occurred. Change 0 = Event has not occurred. 2 Link Status 1 = Event has occurred. Change 0 = Event has not occurred. 1 Automatic Speed 1 = Event has occurred. Downshift 0 = Event has not occurred. 0 MII Interrupt 1 = Interrupt pending. Pending 0 = No interrupt pending.
1. If the management frame preamble is suppressed (MF preamble suppression, register 0, bit 6), it is possible for the PHY to lose synchronization if there is a glitch at the interface. The PHY can recover if a single frame with a preamble is sent to the PHY. The MDIO sync lost interrupt can be used to detect loss of synchronization and thus enable recovery. 2. The MII interrupt pending bit is not masked by interrupt enable bit (interrupt mask register, address 24 bit 0). This bit is inverted and provided as an output on MDINT_N, gated by interrupt enable bit.
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TruePHY ET1011 Gigabit Ethernet Transceiver
Preliminary Data Sheet April 2004
Register Description (continued)
Table 45. PHY Status Register--Address 26 PHY Status Register Bit 15 14:13 Name Reserved Autonegotiation Fault Status Description Type -- RO Default -- 00 Notes -- -- -- 10 = Master/slave autonegotiation fault. 01 = Parallel detect autonegotiation fault. 00 = No autonegotiation fault. 12 Autonegotiation 1 = Autonegotiation is complete. Status 0 = Autonegotiation not complete. www..com 11 MDI-X Status 1 = MDI-X configuration. 0 = MDI configuration. 10 Polarity Status 1 = Polarity is normal (10Base-T only). 0 = Polarity is inverted (10Base-T only). 9:8 Speed Status 11 = Undetermined. 10 = 1000Base-T. 01 = 100Base-TX. 00 = 10Base-T. 7 Duplex Status 1 = Full duplex. 0 = Half duplex. 6 Link Status 1 = Link is up. 0 = Link is down. 5 Transmit Status 1 = PHY is transmitting a packet. 0 = PHY is not transmitting a packet. 4 Receive Status 1 = PHY is receiving a packet. 0 = PHY is not receiving a packet. 3 Collision Status 1 = Collision is occurring. 0 = Collision not occurring. 2 Autonegotiation 1 = Both partners have autonegotiation enabled. Enabled 0 = Both partners do not have autonegotiation enabled. 1 PAUSE Enabled 1 = Link partner advertised PAUSE mode enabled. 0 = Link partner advertised PAUSE mode disabled. 0 Asymmetric Direc- 1 = Link partner advertised direction is symmetric. tion 0 = Link partner advertised that direction is asymmetric.
RO RO RO RO
0 0 1 11
-- -- -- --
RO RO RO RO RO RO
0 0 0 0 0 0
-- -- -- -- -- --
RO RO
0 0
-- --
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Preliminary Data Sheet April 2004
TruePHY ET1011 Gigabit Ethernet Transceiver
Register Description (continued)
Table 46. LED Control Register 1--Address 27 LED Control Register 1 Bit 15:14 13:12 Name Reserved Duplex Indication LED Description -- 00 = Full duplex. 01 = Blink. 10 = On. 11 = Off. 00 = 10Base-T operation. 01 = Blink. 10 = On. 11 = Off. 00 = Collision indication. 01 = Blink. 10 = On. 11 = Off. -- -- 00 = Stretch LED events to 28 ms. 01 = Stretch LED events to 60 ms. 10 = Stretch LED events to 100 ms. 11 = Reserved. 1 = Enable pulse stretching of LED functions: 1000Base-T, 100Base-TX, 10Base-T, link, and duplex. 0 = Disable pulse stretching of LED functions: 1000Base-T, 100Base-TX, 10Base-T, link, and duplex. 1 = Enable pulse stretching of LED functions: transmit activity, receive activity, and collision. 0 = Disable pulse stretching of LED functions: transmit activity, receive activity, and collision. Type -- R/W Default -- 00 Notes -- 1
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11:10
10Base-T LED
R/W
00
1
9:8
Collision Indication LED
R/W
00
1
7:6 5.4 3:2
Reserved Reserved LED Pulse Duration
-- -- R/W
-- -- 00
-- -- --
1
Pulse Stretch 1
R/W
0
--
0
Pulse Stretch 0
R/W
1
--
1. Not applicable in the 68-pin MLCC.
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TruePHY ET1011 Gigabit Ethernet Transceiver
Preliminary Data Sheet April 2004
Register Description (continued)
Table 47. LED Control Register 2--Address 28 LED Control Register 2 Bit Name Description 0000 = 1000Base-T. 0001 = 100Base-TX. 0010 = 10Base-T. 0011 = 1000Base-T on, 100Base-TX blink. 0100 = Link established. 0101 = Transmit. 0110 = Receive. 0111 = Transmit or receive activity. 1000 = Full duplex. 1001 = Collision. 1010 = Link established (on) and activity (blink). 1011 = Link established (on) and receive (blink). 1100 = Full duplex (on) and collision (blink). 1101 = Blink. 1110 = On. 1111 = Off. As per 15:12. As per 15:12. As per 15:12. Type R/W Default 0111 Notes 1 15:12 Transmit/ Receive LED
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11:8 7:4 3:0
Link LED 100Base-TX LED 1000Base-T LED
R/W R/W R/W
0100 0001 0000
-- 1 --
1. Not applicable in the 68-MLCC.
Table 48. Reserved Registers--Addresses 29--31 Reserved Registers Bit 15:0 Name Reserved Description -- Type -- Default -- Notes --
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Preliminary Data Sheet April 2004
TruePHY ET1011 Gigabit Ethernet Transceiver
Electrical Specifications
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Table 49. Absolute Maximum Ratings Parameter
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Symbol AVDDH AVDDL DVDDIO VDD VESD TSTORE
Min -- -- -- -- -- -40
Max 4.2 1.2 4.2 1.2 2000 125
Unit V V V V V C
Supply Voltage (2.5 V analog) Supply Voltage (1.0 V analog) Supply Voltage (3.3 V/2.5 V digital) Supply Voltage (1.0 V digital) ESD Protection Storage Temperature
Recommended Operating Conditions
Table 50. Recommended Operating Conditions Parameter Supply Voltage (2.5 V analog) Supply Voltage (1.0 V analog) Supply Voltage (3.3 V digital)1 Supply Voltage (2.5 V digital)1 Supply Voltage (1.0 V digital) Ambient Operating Temperature Maximum Junction Temperature Thermal Characteristics, 128 TQFP (JDEC 3 in. x 4.5 in. 4-layer PCB, 0 m/s airflow) Thermal Characteristics, 68 MLCC (JDEC 3 in. x 4.5 in. 4-layer PCB, 0 m/s airflow) Symbol AVDDH AVDDL DVDDIO DVDDIO VDD TA TJ TJA TJA Min 2.38 0.95 3.14 2.38 0.95 0 0 TBD TBD Max 2.62 1.05 3.46 2.62 1.05 70 125 TBD TBD Unit V V V V V C C C/W
C/W
1. The part can operate at either 3.3 V (typically for an GMII interface) or 2.5 V (typically for an RGMII interface).
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TruePHY ET1011 Gigabit Ethernet Transceiver
Preliminary Data Sheet April 2004
Electrical Specifications (continued)
Device Electrical Characteristics
Table 51. Device Characteristics--3.3 V Digital I/O Supply (DVDDIO) Parameter Input Low Voltage (GMII input pins) Input Low Voltage (all other digital input pins) Input High Voltage (GMII input pins) Input High Voltage (all other digital input pins)
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Symbol VIL VIL VIH VIH VOL VOL VOH VOH VODIFF VODIFF VODIFF VBIAS
Min -0.3 -0.3 2.0 2.0 -- -- 2.4 2.4 0.67 0.95 2.2 --
Typ -- -- -- -- -- -- -- -- 0.75 1.0 2.5 1.2
Max 0.8 0.8 3.6 3.6 0.4 0.4 -- -- 0.82 1.05 2.8 --
Unit V V V V V V V V V V V V
Output Low Voltage (GMII output pins)
Output Low Voltage (all other digital output pins) Output High Voltage (GMII output pins) Output High Voltage (all other digital output pins) Differential Output Voltage (analog MDI pins 1000Base-T) Differential Output Voltage (analog MDI pins 100Base-TX) Differential Output Voltage (analog MDI pins 10Base-T) Bias Voltage
Table 52. Device Characteristics--2.5 V Digital I/O Supply (DVDDIO) Parameter Input Low Voltage (GMII input pins) Input Low Voltage (all other digital input pins) Input High Voltage (GMII input pins) Input High Voltage (all other digital input pins) Output Low Voltage (GMII output pins) Output Low Voltage (all other digital output pins) Output High Voltage (GMII output pins) Output High Voltage (all other digital output pins) Differential Output Voltage (analog MDI pins 1000Base-T) Differential Output Voltage (analog MDI pins 100Base-TX) Differential Output Voltage (analog MDI pins 10Base-T) Bias Voltage Symbol VIL VIL VIH VIH VOL VOL VOH VOH VODIFF VODIFF VODIFF VBIAS Min -0.3 -0.3 1.7 1.7 -- -- 2.0 2.0 0.67 0.95 2.2 -- Typ -- -- -- -- -- -- -- -- 0.75 1.0 2.5 1.2 Max 0.7 0.7 2.8 2.8 0.4 0.4 -- -- 0.82 1.05 2.8 -- Unit V V V V V V V V V V V V
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Preliminary Data Sheet April 2004
TruePHY ET1011 Gigabit Ethernet Transceiver
Electrical Specifications (continued)
Device Electrical Characteristics (continued)
Table 53. Current Consumption GMII/RGMII 1000Base-T Parameter Supply Voltage (2.5 V analog) Supply Voltage (1.0 V analog) Supply Voltage (3.3 V/2.5 V digital)
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Symbol IAVDDH IAVDDL IDVDDIO IVDD
Condition Tx/Rx random data Tx/Rx random data Tx/Rx random data Tx/Rx random data
Min -- -- -- --
Typ TBD TBD TBD TBD
Max -- -- -- --
Unit mA mA mA mA
Supply Voltage (1.0 V digital)
Table 54. Current Consumption MII/RMII 100Base-TX Parameter Supply Voltage (2.5 V analog) Supply Voltage (1.0 V analog) Supply Voltage (3.3 V/2.5 V digital) Supply Voltage (1.0 V digital) Symbol IAVDDH IAVDDL IDVDDIO IVDD Condition Tx/Rx random data Tx/Rx random data Tx/Rx random data Tx/Rx random data Min -- -- -- -- Typ TBD TBD TBD TBD Max -- -- -- -- Unit mA mA mA mA
Table 55. Current Consumption MII/RMII 10Base-T Parameter Supply Voltage (2.5 V analog) Supply Voltage (1.0 V analog) Supply Voltage (3.3 V/2.5 V digital) Supply Voltage (1.0 V digital) Symbol IAVDDH IAVDDL IDVDDIO IVDD Condition Tx/Rx random data Tx/Rx random data Tx/Rx random data Tx/Rx random data Min -- -- -- -- Typ TBD TBD TBD TBD Max -- -- -- -- Unit mA mA mA mA
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TruePHY ET1011 Gigabit Ethernet Transceiver
Preliminary Data Sheet April 2004
Timing Specification
GMII 1000Base-T Transmit Timing (128-pin TQFP only)
GTX_CLKCYCLE GTX_CLKHIGH GTX_CLKLOW
GTX_CLK
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GTX_CLKFALL
GTX_CLKRISE
TXD[7:0] TX_EN TX_ER GTX_CLKSU GTX_CLKHOLD
Figure 14. GMII 1000Base-T Transmit Timing Table 56. GMII 1000Base-T Transmit Timing Parameter GTX_CLK Cycle Time GTX_CLK High Time GTX_CLK Low Time GTX_CLK Rise Time GTX_CLK Fall Time GMII Input Signal Setup Time to GTX_CLK GMII Input Signal Hold Time to GTX_CLK Symbol GTX_CLKCYCLE GTX_CLKHIGH GTX_CLKLOW GTX_CLKRISE GTX_CLKFALL GTX_CLKSU GTX_CLKHOLD Min 7.5 2.5 2.5 -- -- 2.0 0.0 Typ -- -- -- -- -- -- -- Max 8.5 -- -- 1.0 1.0 -- -- Unit ns ns ns ns ns ns ns
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Preliminary Data Sheet April 2004
TruePHY ET1011 Gigabit Ethernet Transceiver
Timing Specification (continued)
GMII 1000Base-T Receive Timing (128-pin TQFP only)
RX_CLKCYCLE RX_CLKHIGH RX_CLKLOW
RX_CLK
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RX_CLKFALL
RX_CLKRISE
RXD[7:0] RX_EN RX_ER RX_CLKSU RX_CLKHOLD
Figure 15. GMII 1000Base-T Receive Timing Table 57. GMII 1000Base-T Receive Timing Parameter RX_CLK Cycle Time RX_CLK High Time RX_CLK Low Time RX_CLK Rise Time RX_CLK Fall Time GMII Output Signal Setup Time to RX_CLK GMII Output Signal Hold Time to RX_CLK Symbol RX_CLKCYCLE RX_CLKHIGH RX_CLKLOW RTX_CLKRISE RX_CLKFALL RX_CLKSU RX_CLKHOLD Min 7.5 2.5 2.5 -- -- 2.5 0.5 Typ 8.0 -- -- -- -- -- -- Max -- -- -- 1.0 1.0 -- -- Unit ns ns ns ns ns ns ns
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TruePHY ET1011 Gigabit Ethernet Transceiver
Preliminary Data Sheet April 2004
Timing Specification (continued)
RGMII 1000Base-T Transmit Timing
Trace Delay
AT TRANSMITTER
TskewT
TX_CLK GTX_CLK (TXC) TX_CLK AT TRANSMITTER (at transmitter)
TSKEWT
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TXD[8:5][3:0] TXD[8:5][3:0] TXD[7:4][3:0] TXD[3:0]
TXD[7:4][3:0]
TXD[3:0]
TXD[8:5] TXD[8:5] TXD[7:4]
TXD[7:4] TSKEWR
TX_EN TX_CTL (TX_CTL)
TXD[4] TXD[4] TXEN
TX_EN
TXD[9] TXERRTXD[9]
TX_ER
TX_CLK (TXC) GTX_CLK AT RECEIVER ATreceiver) (at RECEIVER
TX_CLK
TskewR
Figure 16. RGMII 1000Base-T Transmit Timing--Trace Delay Table 58. RGMII 1000Base-T Transmit Timing Parameter Data to Clock Output Skew (at transmitter)--Trace Delay1 Data to Clock Input Skew (at receiver)--Trace Delay1 Clock Cycle Duration2 Gigabit3 10Base-T/100Base-TX3 Duty Cycle for Duty Cycle for Symbol TskewT TskewR Tcyc Duty_G Duty_T Tr/Tf Min -500 1 7.2 45 40 -- Typ 0 1.8 8 50 50 -- Max 500 2.6 8.8 55 60 0.75 Unit ps ns ns % % ns
Rise/Fall Time (20%--80%)
1. This implies that PCB design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns and less than 2.0 ns will be added to the associated clock signal. To enable internal delay, see MII register 22 bits 2:0. 2. For 10Base-T and 100Base-TX, Tcyc scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 3. Duty cycle may be shrunk/stretched during speed changes or while transitioning to a received packet's clock domain as long as minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned between.
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TruePHY ET1011 Gigabit Ethernet Transceiver
Timing Specification (continued)
Internal Delay
TX_CLK GTX_CLK (TXC)
TX_CLK AT TRANSMITTER
AT TRANSMITTER (at transmitter)
TX_CLK WITH TXC with internal INTERNAL delay DELAY added ADDED
TSKEWT
TXD[8:5][3:0] TXD[7:4][3:0] TXD[3:0] TXD[8:5] TXD[7:4] TsetupT
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TXD[8:5][3:0] TXD[7:4][3:0]
TXD[3:0]
TXD[8:5] TXD[7:4]
TholdT
TSKEWR
TX_EN (TX_CTL) TXD[4] TXEN TXD[9] TXERR
TX_CTL
TXD[4] TX_EN
TXD[9] TX_ER
GTX_CLK TX_CLK TX_CLK (TXC)
(at receiver) AT RECEIVER
TholdR
AT RECEIVER
TsetupR
Figure 17. RGMII 1000Base-T Transmit Timing--Internal Delay Table 59. RGMII 1000Base-T Transmit Timing Parameter Data to Clock Output Setup (at transmitter--integrated delay)1 Clock to Data Output Hold (at transmitter--integrated delay)1 Data to Clock Input Setup (at receiver--integrated delay)1 Data to Clock Input Setup (at receiver--integrated delay)1 Clock Cycle Duration2 Duty Cycle for Duty Cycle for Gigabit3 10Base-T/100Base-TX3 Symbol TsetupT TholdT TsetupR TholdR Tcyc Duty_G Duty_T Tr/Tf Min 1.2 1.2 1.0 1.0 7.2 45 40 -- Typ 2.0 2.0 2.0 2.0 8 50 50 -- Max -- -- -- -- 8.8 55 60 0.75 Unit ns ns ns ns ns % % ns
Rise/Fall Time (20%--80%)
1. The PHY uses internal delay to compensate by delaying both incoming and outgoing clocks by ~2.0 ns. 2. For 10Base-T and 100Base-TX, Tcyc scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 3. Duty cycle may be shrunk/stretched during speed changes or while transitioning to a received packet's clock domain as long as minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned between.
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TruePHY ET1011 Gigabit Ethernet Transceiver
Preliminary Data Sheet April 2004
Timing Specification (continued)
RGMII 1000Base-T Receive Timing
Trace Delay
AT TRANSMITTER
RX_CLK (RXC) RX_CLK RX_CLK ATtransmitter) (at TRANSMITTER
TskewT
TSKEWT
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RXD[8:5][3:0] RXD[3:0] RXD[7:4][3:0] RXD[3:0] RXD[7:4] RXD[8:5] RXD[3:0] RXD[7:4]
TSKEWR
RX_EN RX_CTL (RX_CTL) RXD[4] RXD[9] RX_ER RXERR
TX_EN RX_DV
RX_CLK RX_CLK (RXC) AT RECEIVER AT RECEIVER (at receiver)
RX_CLK
TskewR
Figure 18. RGMII 1000Base-T Receive Timing--Trace Delay Table 60. RGMII 1000Base-T Receive Timing Parameter Data to Clock Output Skew (at transmitter)--Trace Delay1 Data to Clock Input Skew (at receiver)--Trace Delay1 Clock Cycle Duration2 Gigabit3 10Base-T/100Base-TX3 Duty Cycle for Duty Cycle for Symbol TskewT TskewR Tcyc Duty_G Duty_T Tr/Tf Min -500 1 7.2 45 40 -- Typ 0 1.8 8 50 50 -- Max 500 2.6 8.8 55 60 0.75 Unit ps ns ns % % ns
Rise/Fall Time (20%--80%)
1. This implies that PCB design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns and less than 2.0 ns will be added to the associated clock signal. To enable internal delay, see MII register 22 bits 2:0. 2. For 10Base-T and 100Base-TX, Tcyc scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 3. Duty cycle may be shrunk/stretched during speed changes or while transitioning to a received packet's clock domain as long as minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned between.
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Agere Systems Inc.
Preliminary Data Sheet April 2004
TruePHY ET1011 Gigabit Ethernet Transceiver
Timing Specification (continued)
Internal Delay
RX_CLK AT TRANSMITTER
RX_CLK (RXC) RX_CLK (at transmitter) AT TRANSMITTER
RX_CLK WITH RXC with INTERNAL internal delay DELAY added ADDED
TSKEWT
RXD[8:5][3:0] RXD[8:5][3:0] rXD[7:4][3:0] RXD[7:4][3:0] RXD[3:0] RXD[8:5] RXD[7:4] TsetupT
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RXD[3:0]
RXD[7:4]
RXD[3:0]
TholdT
TSKEWR
RX_EN (RX_CTL) RXD[4] RX_DV RXD[9] RXERR
RX_CTL
TX_EN
RX_ER
RX_CLK RX_CLK RX_CLK (RXC) AT RECEIVER (at receiver)
TholdR
AT RECEIVER
TsetupR
Figure 19. RGMII 1000Base-T Receive Timing--Internal Delay Table 61. RGMII 1000Base-T Receive Timing Parameter Data to Clock Output Setup (at transmitter--integrated delay)1 Clock to Data Output Hold (at transmitter--integrated delay)1 Data to Clock Input Setup (at receiver--integrated delay)1 Data to Clock Input Setup (at receiver--integrated delay)1 Clock Cycle Duration2 Duty Cycle for Gigabit3 Duty Cycle for 10Base-T/100Base-TX3 Rise/Fall Time (20%--80%) Symbol TsetupT TholdT TsetupR TholdR Tcyc Duty_G Duty_T Tr/Tf Min 1.2 1.2 1.0 1.0 7.2 45 40 -- Typ 2.0 2.0 2.0 2.0 8 50 50 -- Max -- -- -- -- 8.8 55 60 0.75 Unit ns ns ns ns ns % % ns
1. The PHY uses internal delay to compensate by delaying both incoming and outgoing clocks by ~2.0 ns. 2. For 10Base-T and 100Base-TX, Tcyc scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 3. Duty cycle may be shrunk/stretched during speed changes or while transitioning to a received packet's clock domain as long as minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned between.
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TruePHY ET1011 Gigabit Ethernet Transceiver
Preliminary Data Sheet April 2004
Timing Specification (continued)
MII 100Base-TX Transmit Timing
TX_CLKCYCLE TX_CLKHIGH TX_CLKLOW
TX_CLK
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TX_CLKFALL
TX_CLKRISE
TXD[3:0] TX_EN TX_ER1 TX_CLKSU
1. TX_ER is not available on the 68-pin MLCC.
TX_CLKHOLD
Figure 20. MII 100Base-TX Transmit Timing Table 62. MII 100Base-TX Transmit Timing Parameter TX_CLK Cycle Time TX_CLK High Time TX_CLK Low Time TX_CLK Rise Time TX_CLK Fall Time MII Input Signal Setup Time to TX_CLK MII Input Signal Hold Time to TX_CLK Symbol TX_CLKCYCLE TX_CLKHIGH TX_CLKLOW TX_CLKRISE TX_CLKFALL TX_CLKSU TX_CLKHOLD Min -- -- -- -- -- 15 0 Typ 40 20 20 -- -- -- -- Max -- -- -- 5 5 -- -- Unit ns ns ns ns ns ns ns
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Agere Systems Inc.
Preliminary Data Sheet April 2004
TruePHY ET1011 Gigabit Ethernet Transceiver
Timing Specification (continued)
MII 100Base-TX Receive Timing
RX_CLKCYCLE RX_CLKHIGH RX_CLKLOW
RX_CLK
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RX_CLKFALL
RX_CLKRISE
RXD[3:0] RX_EN RX_ER RX_CLKSU RX_CLKHOLD
Figure 21. MII 100Base-TX Receive Timing Table 63. MII 100Base-TX Receive Timing Parameter RX_CLK Cycle Time RX_CLK High Time RX_CLK Low Time RX_CLK Rise Time RX_CLK Fall Time MII Output Signal Setup Time to RX_CLK MII Output Signal Hold Time to RX_CLK Symbol RX_CLKCYCLE RX_CLKHIGH RX_CLKLOW RTX_CLKRISE RX_CLKFALL RX_CLKSU RX_CLKHOLD Min -- -- -- -- -- 10 10 Typ 40 20 20 1 1 -- -- Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns
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TruePHY ET1011 Gigabit Ethernet Transceiver
Preliminary Data Sheet April 2004
Timing Specification (continued)
MII 10Base-T Transmit Timing
TX_CLKCYCLE TX_CLKHIGH TX_CLKLOW
TX_CLK www..com TX_CLKFALL TX_CLKRISE
TXD[3:0] TX_EN TX_ER TX_CLKSU TX_CLKHOLD
Figure 22. MII 10Base-T Transmit Timing Table 64. MII 10Base-T Transmit Timing Parameter TX_CLK Cycle Time TX_CLK High Time TX_CLK Low Time TX_CLK Rise Time TX_CLK Fall Time MII Input Signal Setup Time to TX_CLK MII Input Signal Hold Time to TX_CLK Symbol TX_CLKCYCLE TX_CLKHIGH TX_CLKLOW TX_CLKRISE TX_CLKFALL TX_CLKSU TX_CLKHOLD Min -- -- -- -- -- 15 10 Typ 400 200 200 1 1 -- -- Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns
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Agere Systems Inc.
Preliminary Data Sheet April 2004
TruePHY ET1011 Gigabit Ethernet Transceiver
Timing Specification (continued)
MII 10Base-T Receive Timing
RX_CLKCYCLE RX_CLKHIGH RX_CLKLOW
RX_CLK
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RX_CLKFALL
RX_CLKRISE
RXD[3:0] RX_EN RX_ER RX_CLKSU RX_CLKHOLD
Figure 23. MII 10Base-T Receive Timing Table 65. MII 10Base-T Receive Timing Parameter RX_CLK Cycle Time RX_CLK High Time RX_CLK Low Time RX_CLK Rise Time RX_CLK Fall Time MII Output Signal Setup Time to RX_CLK MII Output Signal Hold Time to RX_CLK Symbol RX_CLKCYCLE RX_CLKHIGH RX_CLKLOW RTX_CLKRISE RX_CLKFALL RX_CLKSU RX_CLKHOLD Min -- -- -- -- -- 10 10 Typ 400 200 200 1 1 -- -- Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns
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TruePHY ET1011 Gigabit Ethernet Transceiver
Preliminary Data Sheet April 2004
Timing Specification (continued)
Serial Management Interface Timing
MDCCYCLE MDCHIGH MDCLOW
MDC
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MDCRISE
MDIO (INPUT) MDCSU MDCHOLD
MDC
MDIO (OUTPUT) MDCDELAY
Figure 24. Serial Management Interface Timing Table 66. Serial Management Interface Timing Parameter MDC Cycle Time MDC High Time MDC Low Time MDC Rise Time MDC Fall Time MDIO Signal Setup Time to MDC MDIO Signal Hold Time to MDC MDIO Delay Time from MDC Symbol MDCCYCLE MDCHIGH MDCLOW MDCRISE MDCFALL MDCSU MDCHOLD MDCDELAY Min 100 40 40 -- -- 10 10 -- Typ -- -- -- -- -- -- -- -- Max -- -- -- 5 5 -- -- 80 Unit ns ns ns ns ns ns ns ns
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Agere Systems Inc.
Preliminary Data Sheet April 2004
TruePHY ET1011 Gigabit Ethernet Transceiver
Timing Specification (continued)
Reset Timing
RESETPULSE_LEN RESETCFG_READ
RESET_N
RESETRISE
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LED_xx
LED pins are Inputs
LED pins are Outputs
SYSCLK
COMAPULSE_LEN
COMACFG_READ
COMA
COMAFALL
LED_xx
LED pins are Inputs
LED pins are Outputs
SYSCLK
COMATO_SYSCLK
Figure 25. Reset Timing Table 67. Reset Timing Parameter RESET_N Pulse Length RESET_N Rise Time RESET_N Deassertion to Configuration Read COMA Pulse Length COMA Fall Time COMA Deassertion to SYS_CLK Valid COMA Deassertion to Configuration Read Agere Systems Inc. Symbol RESETPULSE_LEN RESETRISE RESETCFG_READ COMAPULSE_LEN COMAFALL COMATO_SYSCLK COMACFG_READ Min 1.0 -- -- 1.0 -- -- -- Typ -- 1.0 -- -- 1.0 1.0 -- Max -- -- 5.0 -- -- -- 5.0 Unit s ns ms s ns ns ms 73
TruePHY ET1011 Gigabit Ethernet Transceiver
Preliminary Data Sheet April 2004
Timing Specification (continued)
Clock Timing
XTAL_1CYCLE XTAL_1HIGH XTAL_1LOW
www..com XTAL_1
XTAL_1FALL
XTAL_1RISE
Figure 26. Clock Timing Table 68. Clock Timing Parameter XTAL_1 Cycle Time XTAL_1 High Time XTAL_1 Low Time XTAL_1 Rise Time XTAL_1 Fall Time XTAL_1 Input Clock Jitter (RMS) XTAL_1 Input Clock Frequency XTAL_1 Input Clock Accuracy Symbol XTAL_1CYCLE XTAL_1HIGH XTAL_1LOW XTAL_1RISE XTAL_1FALL -- -- -- Min 39.998 15 15 -- -- -- -- -- Typ 40 20 20 -- -- -- 25 -- Max 40.002 25 25 3 3 20 -- 50 Unit ns ns ns ns ns ps MHz ppm
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Agere Systems Inc.
Preliminary Data Sheet April 2004
TruePHY ET1011 Gigabit Ethernet Transceiver
Timing Specification (continued)
JTAG Timing
TCKCYCLE TCKHIGH TCKLOW
TCK
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TCKFALL
TCKRISE
TDI TMS TCKHOLD
TCKSU
TDO
TCKDELAY
Figure 27. JTAG Timing Table 69. JTAG Timing Parameter TCK Cycle Time TCK High Time TCK Low Time TCK Rise Time TCK Fall Time TDI, TMS Setup Time to TCK TDI, TMS Hold Time to TCK TDO Delay Time from TCK Symbol TCKCYCLE TCKHIGH TCKLOW TCKRISE TCKFALL TCKSU TCKHOLD TCKDELAY Min 20 10 10 -- -- 2.7 0.8 -- Typ -- -- -- 1 1 -- -- -- Max -- -- -- -- -- -- -- 8.1 Unit ns ns ns ns ns ns ns ns
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TruePHY ET1011 Gigabit Ethernet Transceiver
Preliminary Data Sheet April 2004
Package Diagram, 128-Pin TQFP
16.00 0.20 14.00 0.20 PIN #1 IDENTIFIER ZONE
128 103
1
102
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20.00 0.20 22.00 0.20
38
65
39
64
DETAIL A
DETAIL B
1.40 0.05 1.60 MAX SEATING PLANE 0.08
0.50 TYP 1.00 REF
0.05/0.15
0.25 GAGE PLANE SEATING PLANE 0.45/0.75 DETAIL A 0.19/0.27 0.08
M
0.106/0.200
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Agere Systems Inc.
Preliminary Data Sheet April 2004
TruePHY ET1011 Gigabit Ethernet Transceiver
Package Diagram, 68-Pin MLCC (Dimensions are in millimeters.)
Note: Package outlines are unofficial and for reference only.
5.80
2.90
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2.90
5.80
0.50 0.42 0.55 8.00
0.23
0.42
0.20 REF
0.01
0.80
0.65
4.87 5.00
9.75
10.0
0.23
0.01
10.00
9.75
4.87
5.00
PIN #1 IDENTIFIER
Agere Systems Inc.
0.50
0.50
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TruePHY ET1011 Gigabit Ethernet Transceiver
Preliminary Data Sheet April 2004
Ordering Information
Table 70. Chip Set Names and Part Numbers Device ET1011 ET1011 Description Ethernet Transceiver Ethernet Transceiver Package 128-pin TQFP 68-pin MLCC Part Number ET1011-128T ET1011-68M-D Comcode 7000497740 700066380
Related Product Documentation
Table 71. Related Product Documentation Device
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Description Gigabit Ethernet Transceiver Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch Gigabit Ethernet Octal PHY Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch Single-Chip 28 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch Single-Chip 28 x 1 Gbit/s Layer 2+ Ethernet Switch Single-Chip 48 x 1 Gbit/s Layer 2+ Ethernet Switch
Document Type Document Number Data Sheet Data Sheet Data Sheet Product Brief Product Brief Product Brief Product Brief DS04-017GPHY TBD DS04-056GPHY PB04-039GWSC PB04-049GWSC PB04-047GWSC PB04-048GWSC
ET1010 ET4101
ET1081 ET4101 ET4100 ET4000 ET4001
IEEE is a registered trademark of the Institute of Electrical and Electronics Engineers, Inc. Magic Packet is a registered trademark of Advanced Micro Devices, Inc.
For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-54614688 (Shanghai), (86) 21-25881122 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere is a registered trademark of Agere Systems Inc. Agere Systems and the Agere logo are trademarks of Agere Systems Inc. TruePHY is a trademark of Agere Systems Inc.
Copyright (c) 2004 Agere Systems Inc. All Rights Reserved
April 2004 DS04-063GPHY-2 (Replaces DS04-063GPHY-1.1)

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